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C
F. Ren and Marković, D. , “A Configurable 12–237 kS/s 12.8 mW Sparse-Approximation Engine for Mobile Data Aggregation of Compressively Sampled Physiological Signals”, IEEE Journal of Solid-State Circuits, vol. 51, no. 1, pp. 68-78, 2016. (3.07 MB)
F. Ren and Marković, D. , “A Configurable 12-to-237KS/s 12.8 mW Sparse-approximation Engine for Mobile ExG Data Aggregation”, Proceedings of the 2015 IEEE International Solid-State Circuits Conference (ISSCC). IEEE, pp. 68-78, 2015. (6.94 MB)
H. Huang, Yu, H. , Zhuo, C. , and Ren, F. , “A Compressive-sensing based Testing Vehicle for 3D TSV Pre-bond and Post-bond Testing Data”, International Symposium on Physical Design (ISPD). pp. 19-25, 2016. (1.21 MB)
B
Y. I. Li, Zhang, S. , Zhou, X. , and Ren, F. , “Build a Compact Binary Neural Network through Bit-level Sensitivity and Data Pruning”, Neurocomputing, vol. 398, pp. 45-54, 2020. (1.91 MB)
F. Ren, Park, H. , Dorrance, R. , Toriyama, Y. , Yang, C. - K. K. , and Marković, D. , “A Body-voltage-sensing-based Short Pulse Reading Circuit for Spin-torque Transfer RAMs (STT-RAMs)”, Proceedings of the 2012 13th International Symposium on Quality Electronic Design (ISQED). IEEE, pp. 275-282, 2012. (559.47 KB)
K. - L. Wang, Yang, C. - K. K. , Markovic, D. , and Ren, F. , “Body Voltage Sensing Based Short Pulse Reading Circuit”, PCT/US2012/056136, 2014.
Y. I. Li and Ren, F. , “BNN Pruning: Pruning Binary Neural Network Guided by Weight Flipping Frequency”, International Symposium on Quality Electronic Design (ISQED). Santa Clara, CA, 2020. (186.31 KB)
Z. Liu, Li, Y. , Ren, F. , and Yu, H. , “A Binary Convolutional Encoder-decoder Network for Real-time Natural Scene Text Processing”, The 1st International Workshop on Efficient Methods for Deep Neural Networks - Conference on Neural Information Processing Systems (NIPS). 2016. (773.3 KB)
A
Z. Zhang, Trindade, B. Machado, Green, M. , Yu, Z. , Pawlowicz, C. , and Ren, F. , “Automatic Error Detection in Integrated Circuits Image Segmentation: A Data-driven Approach”, The 48th IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP'23). Rhodes Island, Greece, 2023. (501.02 KB)
S. Biookaghazadeh, Zhao, M. , and Ren, F. , “Are FPGAs Suitable for Edge Computing?”, The USENIX Workshop on Hot Topics in Edge Computing (HotEdge '18). BOSTON, MA, 2018. (363.22 KB)
H. Park, Dorrance, R. , Amin, A. , Ren, F. , Marković, D. , and Yang, C. K. Ken, “Analysis of STT-RAM Cell Design With Multiple MTJs Per Access”, Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH). IEEE Computer Society, pp. 53-58, 2011. (320.88 KB)
9
B. Hu, Ren, F. , Chen, Z. - Z. , Jiang, X. , and Chang, M. - C. Frank, “9-bit time–digital-converter-assisted compressive-sensing analogue–digital-converter with 4 GS/s equivalent speed”, IET Electronics Letters, vol. 52, no. 6, pp. 430-432, 2016. (511.29 KB)
8
B. Hu, Ren, F. , Chen, Z. - Z. , Jiang, X. , and Chang, M. - C. Frank, “An 8-Bit Compressive Sensing ADC With 4GS/s Equivalent Speed Utilizing Self-Timed Pipeline SAR-Binary-Search”, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 63, no. 10, pp. 934-938, 2016. (1.8 MB)
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Y. I. Li, Liu, Z. , Liu, W. , Jiang, Y. , Wang, Y. , Goh, W. Ling, Yu, H. , and Ren, F. , “A 34-FPS 698-GOP/s/W Binarized Deep Neural Network-based Natural Scene Text Interpretation Accelerator for Mobile Edge Computing”, IEEE Transactions on Industrial Electronics (TIE), vol. 66, no. 9, pp. 7407-7416, 2019. (3.34 MB)

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