CEN571 Hardware Acceleration and FPGA Computing

Course Description:

This is a research-oriented course jointly offered in the schools of CIDSE and ECEE to foster cross-disciplinary interactions among students with diverse focus areas. It aims to bring together graduate students with a background in either computational algorithms or hardware design to collaboratively work on challenging class projects that focus on designing and optimizing hardware accelerators for computationally intensive algorithms to advance real-life applications. The topics in this course include energy delay models, timing, circuit optimization, architecture techniques, architecture flexibility, DSP arithmetic, data flow control, and FPGA essentials.

The lectures and laboratory sessions seek to impart the following to students:

Basic knowledge of FPGA architecture and DSP arithmetic.
Essential skills for mapping a high-level description of algorithms into FPGA or ASIC design.
Circuit techniques for optimizing energy and delay.
Architecture transformation techniques for optimizing energy and area.
Deep understanding about the intricate tradeoff between throughput, energy, and area associated with various design choices.
Hands-on experience of designing and optimizing a hardware accelerator for computationally intensive algorithms to advance a broad range of applications, such as bioinformatics, multimedia signal processing, artificial intelligence, etc.

Offerings:

Fall 2020

Lecture Schedule:

On Demand (Online Recording)

Lab Location:

Online

Classroom:

Online

Instructor Office Hours:

W 7:15am-8:30am, Mountain Standard Time (MST), UTC -7

Localtion:

Zoom Link