@article {9999,
	title = {An 8-Bit Compressive Sensing ADC With 4GS/s Equivalent Speed Utilizing Self-Timed Pipeline SAR-Binary-Search},
	journal = {IEEE Transactions on Circuits and Systems II: Express Briefs},
	volume = {63},
	year = {2016},
	month = {10/2016},
	pages = {934-938},
	abstract = {<p><span style="font-size: 16px;">This brief presents a 65nm CMOS single-channel 8- bit ADC compatible for energy-efficient high-speed Compressive Sensing (CS) and Nyquist Sampling (NS). A self-timed pipeline two-stage SAR-Binary-Search (BS) architecture is proposed and integrated with a 4GHz random-matrix clock generator, enabling a physical sampling speed up to 500MS/s with 40.2dB SNDR in NS-mode, and an equivalent speed up to 4GS/s with 36.2dB SNDR in CS-mode, leading to a FOM of 239fJ/conversion-step and 71fJ/conversion-step respectively. A Passive-charge-sharing (PCS) with open-loop (OL) residue-amplifier (RA) technique is proposed to boost the maximum physical sampling speed and the equivalent CS acquisition bandwidth. A reference-voltage fitting calibration scheme is applied to pre-distort inter-stage errors.</span></p>},
	keywords = {psclab},
	author = {Boyu Hu and Fengbo Ren and Zuow-Zun Chen and Xicheng Jiang and Mau-Chung Frank Chang}
}
