Title | An 8-Bit Compressive Sensing ADC With 4GS/s Equivalent Speed Utilizing Self-Timed Pipeline SAR-Binary-Search |
Publication Type | Journal Article |
Year of Publication | 2016 |
Authors | Hu, B, Ren, F, Chen, Z-Z, Jiang, X, Chang, M-CFrank |
Journal | IEEE Transactions on Circuits and Systems II: Express Briefs |
Volume | 63 |
Issue | 10 |
Pagination | 934-938 |
Date Published | 10/2016 |
Keywords (or New Research Field) | psclab |
Abstract | This brief presents a 65nm CMOS single-channel 8- bit ADC compatible for energy-efficient high-speed Compressive Sensing (CS) and Nyquist Sampling (NS). A self-timed pipeline two-stage SAR-Binary-Search (BS) architecture is proposed and integrated with a 4GHz random-matrix clock generator, enabling a physical sampling speed up to 500MS/s with 40.2dB SNDR in NS-mode, and an equivalent speed up to 4GS/s with 36.2dB SNDR in CS-mode, leading to a FOM of 239fJ/conversion-step and 71fJ/conversion-step respectively. A Passive-charge-sharing (PCS) with open-loop (OL) residue-amplifier (RA) technique is proposed to boost the maximum physical sampling speed and the equivalent CS acquisition bandwidth. A reference-voltage fitting calibration scheme is applied to pre-distort inter-stage errors. |
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