@article {9999,
	title = {9-bit time{\textendash}digital-converter-assisted compressive-sensing analogue{\textendash}digital-converter with 4 GS/s equivalent speed},
	journal = {IET Electronics Letters},
	volume = {52},
	year = {2016},
	month = {03/2016},
	pages = {430-432},
	abstract = {<p><span style="font-family: Arial, {\textquoteright}Helvetica Neue{\textquoteright}, Helvetica, sans-serif; line-height: 19.2px;">A novel 9-bit time{\textendash}digital-converter (TDC)-assisted analogue{\textendash}digital-converter (ADC) supporting energy-efficient high-speed compressive-sensing (CS) operation is presented. With a voltage{\textendash}time-converter serving as the cross-domain residue conveyer, the proposed two-stage self-timed pipeline ADC architecture hybrids a voltage-domain comparator-interleaved successive-approximation (SAR) ADC front-end and a time-domain locally readjusted folding two-dimensional Vernier TDC back-end. Implemented in 65 nm CMOS technology, the prototype benefits from both the CS-enabled sub-Nyquist operation and the hybrid quantisation scheme, leading up to 4 GS/s equivalent speed with 34.2 dB signal-noise-distortion-ratio (SNDR) and a figure-of-merit (FOM) of 101 fJ/conversion step.</span></p>},
	keywords = {psclab},
	author = {Boyu Hu and Fengbo Ren and Zuow-Zun Chen and Xicheng Jiang and Mau-Chung Frank Chang}
}
