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F. Ren, Dorrace, R. , Xu, W. , and Marković, D. , A Single-precision Compressive Sensing Signal Reconstruction Engine on FPGAs, Proceedings of the 23rd International Conference on Field Programmable Logic and Applications (FPL). IEEE, pp. 1-4, 2013. (358.12 KB)
F. Ren, Zhang, C. , Liu, L. , Xu, W. , Owall, V. , and Marković, D. , A Square-Root-Free Matrix Decomposition Method for Energy-Efficient Least Square Computation on Embedded Systems, IEEE Embedded Systems Letters, vol. 6, no. 4, pp. 73–76, 2014. (912.74 KB)
Z. Liu, Li, Y. I. , Ren, F. , Yu, H. , and Goh, W. , SqueezedText: A Real-time Scene Text Recognition by Binary Convolutional Encoder-decoder Network, The AAAI Conference on Artificial Intelligence (AAAI). New Orleans, Louisana, pp. 7194-7201, 2018. (1.49 MB)
L. Cheng, Xu, W. , Ren, F. , Gong, F. , Gupta, P. , and He, L. , Statistical Timing and Power Analysis of VLSI Considering Non-linear Dependence, the VLSI Journal Integration, vol. 47, no. 4, pp. 487–498, 2014. (845.26 KB)
M. Hassan Quraishi, Bank-Tavakoli, E. , and Ren, F. , A Survey of System Architectures and Techniques for FPGA Virtualization, IEEE Transactions on Parallel and Distributed Systems, vol. 32, no. 9, pp. 2216-2230, 2021. (435.22 KB)
A. Dua, Li, Y. I. , and Ren, F. , Systolic-CNN: An OpenCL-defined Scalable Run-time-flexible FPGA Accelerator Architecture for Accelerating Convolutional Neural Network Inference in Cloud/Edge Computing, 2020.
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F. Ren and Marković, D. , True Energy-performance Analysis Of The MTJ-based Logic-in-memory Architecture (1-bit Full Adder), IEEE Transactions on Electron Devices, vol. 57, no. 5, pp. 1023–1028, 2010. (632.59 KB)

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