Scalability And Design-space Analysis of A 1T-1MTJ Memory Cell

TitleScalability And Design-space Analysis of A 1T-1MTJ Memory Cell
Publication TypeConference Proceedings
Year of Publication2011
AuthorsDorrance, R, Ren, F, Toriyama, Y, Amin, A, Yang, C-KK, Marković, D
Conference NameProceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)
Date Published01/2011
Keywords (or New Research Field)psclab

This paper introduces a design-space feasibility region as a function of MTJ characteristics and memory target specifications. The sensitivity of the design space is analyzed for scaling of both MTJ and underlying transistor technology. Design points for improved yield, density, and memory performance can be extracted for 90nm down to 32nm processes based on measured MTJ devices. To achieve flash-like densities in upcoming 22nm and 16nm technology nodes, scaling of the critical switching current density is required.