Scalable and Parameterized VLSI Architecture for Compressive Sensing Sparse Approximation

TitleScalable and Parameterized VLSI Architecture for Compressive Sensing Sparse Approximation
Publication TypePatent
Year of Publication2015
AuthorsMarkovic, D, Ren, F
Application NumberUS14/446,272
Date PublishedJan 29, 2015
Patent NumberUS10073701B2
Keywords (or New Research Field)psclab
Abstract

Systems and methods for implementing a scalable very-large-scale integration (VLSI) architecture to perform compressive sensing (CS) hardware reconstruction for data signals in accordance with embodiments of the invention are disclosed. The VLSI architecture is optimized for CS signal reconstruction by implementing a reformulation of the orthogonal matching pursuit (OMP) process and utilizing architecture resource sharing techniques. Typically, the VLSI architecture is a CS reconstruction engine that includes a vector and scalar computation cores where the cores can be time-multiplexed (via dynamic configuration) to perform each task associated with OMP. The vector core includes configurable processing elements (PEs) connected in parallel. Further, the cores can be linked by data-path memories, where complex data flow of OMP can be customized utilizing local memory controllers synchronized by a top-level finite-state machine. The computing resources (cores and data-paths) can be reused across the entire OMP process resulting in optimal utilization of the PEs.

URLhttps://www.google.com/patents/US20150032990