Publication

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Conference Proceedings
H. Park, Dorrance, R. , Amin, A. , Ren, F. , Marković, D. , and Yang, C. K. Ken, Analysis of STT-RAM Cell Design With Multiple MTJs Per Access, Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH). IEEE Computer Society, pp. 53-58, 2011. (320.88 KB)
M. Courbariaux, Bengio, Y. , and David, J. - P. , Binaryconnect: Training deep neural networks with binary weights during propagations, Advances in Neural Information Processing Systems. pp. 3123–3131, 2015.
F. Ren, Park, H. , Dorrance, R. , Toriyama, Y. , Yang, C. - K. K. , and Marković, D. , A Body-voltage-sensing-based Short Pulse Reading Circuit for Spin-torque Transfer RAMs (STT-RAMs), Proceedings of the 2012 13th International Symposium on Quality Electronic Design (ISQED). IEEE, pp. 275-282, 2012. (559.47 KB)
T. Chen, Du, Z. , Sun, N. , Wang, J. , Wu, C. , Chen, Y. , and Temam, O. , Diannao: A small-footprint high-throughput accelerator for ubiquitous machine-learning, ACM Sigplan Notices, vol. 49. ACM, pp. 269–284, 2014.
T. S. Czajkowski, Aydonat, U. , Denisenko, D. , Freeman, J. , Kinsner, M. , Neto, D. , Wong, J. , Yiannacouras, P. , and Singh, D. P. , From OpenCL to high-performance hardware on FPGAs, Field Programmable Logic and Applications (FPL), 2012 22nd International Conference on. IEEE, pp. 531–534, 2012.
Y. I. Li, Dua, A. , and Ren, F. , Light-Weight RetinaNet for Object Detection on Edge Devices, The 2020 IEEE World Forum on Internet of Things (WF-IoT'20). New Orleans, Louisiana, 2020. (2.43 MB)
R. Dorrance, Ren, F. , Toriyama, Y. , Amin, A. , Yang, C. - K. K. , and Marković, D. , Scalability And Design-space Analysis of A 1T-1MTJ Memory Cell, Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH). IEEE, pp. 32-36, 2011. (1.1 MB)
R. Dorrance, Ren, F. , and Marković, D. , A Scalable Sparse Matrix-vector Multiplication Kernel for Energy-efficient Sparse-BLAS on FPGAs, Proceedings of the 2014 ACM/SIGDA International Symposium on Field-programmable Gate Arrays (FPGA). ACM, pp. 161-170, 2014. (558.35 KB)
F. Ren, Dorrace, R. , Xu, W. , and Marković, D. , A Single-precision Compressive Sensing Signal Reconstruction Engine on FPGAs, Proceedings of the 23rd International Conference on Field Programmable Logic and Applications (FPL). IEEE, pp. 1-4, 2013. (358.12 KB)
H. Palangi, Ward, R. K. , and Deng, L. , Using deep stacking network to improve structured compressed sensing with Multiple Measurement Vectors., ICASSP. pp. 3337–3341, 2013.
Journal Article
S. Nam, Davies, M. E. , Elad, M. , and Gribonval, R. , The cosparse analysis model and algorithms, Applied and Computational Harmonic Analysis, vol. 34, pp. 30–56, 2013.
H. Palangi, Ward, R. K. , and Deng, L. , Distributed Compressive Sensing: A Deep Learning Approach., IEEE Trans. Signal Processing, vol. 64, pp. 4504–4518, 2016.
D. L. Donoho and Tsaig, Y. , Fast solution of $$\backslash$ell \_ $\$1$\$ $-norm minimization problems when the solution may be sparse, IEEE Transactions on Information Theory, vol. 54, pp. 4789–4812, 2008.
W. Dally, High-performance hardware for machine learning, NIPS Tutorial, 2015.
M. A. Davenport, Duarte, M. F. , Eldar, Y. C. , and Kutyniok, G. , Introduction to compressed sensing, preprint, vol. 93, p. 2, 2011.
M. A. Davenport, Duarte, M. F. , Eldar, Y. C. , and Kutyniok, G. , Introduction to compressed sensing, preprint, vol. 93, p. 2, 2011.
M. A. Davenport, Duarte, M. F. , Eldar, Y. C. , and Kutyniok, G. , Introduction to compressed sensing, preprint, vol. 93, p. 2, 2011.
M. A. Davenport, Duarte, M. F. , Eldar, Y. C. , and Kutyniok, G. , Introduction to compressed sensing, preprint, vol. 93, p. 2, 2011.
J. Martin Duarte-Carvajalino and Sapiro, G. , Learning to sense sparse signals: Simultaneous sensing matrix and sparsifying dictionary optimization, IEEE Transactions on Image Processing, vol. 18, pp. 1395–1408, 2009.
A. Putnam, Caulfield, A. M. , Chung, E. S. , Chiou, D. , Constantinides, K. , Demme, J. , Esmaeilzadeh, H. , Fowers, J. , Gopal, G. Prashanth, Gray, J. , and , , A reconfigurable fabric for accelerating large-scale datacenter services, IEEE Micro, vol. 35, pp. 10–22, 2015.
R. Dorrance, Ren, F. , Toriyama, Y. , Hafez, A. Amin, Yang, C. - K. K. , and Marković, D. , Scalability and Design-space Analysis of A 1T-1MTJ Memory Cell For STT-RAMs, IEEE Transactions on Electron Devices, vol. 59, no. 4, pp. 878–887, 2012. (1.1 MB)
Thesis
A. Dua, Hardware Acceleration of Video Analytics on FPGA Using OpenCL, Arizona State University, Tempe, 2019. (2.83 MB)