Publication

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Journal Article
F. Ren, Xu, W. , and Marković, D. , “Scalable and Parameterised VLSI Architecture for Efficient Sparse Approximation in FPGAs And SoCs”, IET Electronics Letters, vol. 49, no. 23, pp. 1440–1441, 2013. (154.45 KB)
F. Ren, Zhang, C. , Liu, L. , Xu, W. , Owall, V. , and Marković, D. , “A Square-Root-Free Matrix Decomposition Method for Energy-Efficient Least Square Computation on Embedded Systems”, IEEE Embedded Systems Letters, vol. 6, no. 4, pp. 73–76, 2014. (912.74 KB)
L. Cheng, Xu, W. , Ren, F. , Gong, F. , Gupta, P. , and He, L. , “Statistical Timing and Power Analysis of VLSI Considering Non-linear Dependence”, the VLSI Journal Integration, vol. 47, no. 4, pp. 487–498, 2014. (845.26 KB)
M. Hassan Quraishi, Bank-Tavakoli, E. , and Ren, F. , “A Survey of System Architectures and Techniques for FPGA Virtualization”, IEEE Transactions on Parallel and Distributed Systems, vol. 32, no. 9, pp. 2216-2230, 2021. (435.22 KB)
F. Ren and Marković, D. , “True Energy-performance Analysis Of The MTJ-based Logic-in-memory Architecture (1-bit Full Adder)”, IEEE Transactions on Electron Devices, vol. 57, no. 5, pp. 1023–1028, 2010. (632.59 KB)
Miscellaneous
R. Rangaswami, Biookaghazadeh, S. , and Lyons, S. , “Techniques and systems for local independent failure domains”. 2017.
Patent
K. - L. Wang, Yang, C. - K. K. , Markovic, D. , and Ren, F. , “Body Voltage Sensing Based Short Pulse Reading Circuit”, PCT/US2012/056136, 2014.
F. Ren, Xu, K. , and Zhang, Z. , “LAPRAN: A SCALABLE LAPLACIAN PYRAMID RECONSTRUCTIVE ADVERSARIAL NETWORK FOR FLEXIBLE COMPRESSIVE SENSING RECONSTRUCTION”, 16/745,817, 2020.
F. Ren and Xu, K. , “Real time end-to-end learning system for a high frame rate video compressive sensing network”, US16/165,568, 2019.
D. Markovic and Ren, F. , “Scalable and Parameterized VLSI Architecture for Compressive Sensing Sparse Approximation”, US14/446,272, 2015.
Presentation
B. Li and Ren, F. , “Enabling Deep Learning for Edge Computing”. 2019. (5.52 MB)
Report
A. Dua, Li, Y. I. , and Ren, F. , “Systolic-CNN: An OpenCL-defined Scalable Run-time-flexible FPGA Accelerator Architecture for Accelerating Convolutional Neural Network Inference in Cloud/Edge Computing”, 2020.
Thesis
F. Ren, “Energy-performance Characterization of CMOS/Magnetic Tunnel Junction (MTJ) Hybrid Logic Circuits”, University of California, Los Angeles, Los Angeles, 2011. (1.05 MB)
F. Ren, “A Scalable VLSI Architecture for Real-Time and Energy-Efficient Sparse Approximation in Compressive Sensing Systems”, University of California, Los Angeles, Los Angeles, 2015. (5.71 MB)

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