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D
A. Dua, Li, Y. I. , and Ren, F. , Systolic-CNN: An OpenCL-defined Scalable Run-time-flexible FPGA Accelerator Architecture for Accelerating Convolutional Neural Network Inference in Cloud/Edge Computing, 2020.
R. Dorrance, Ren, F. , Toriyama, Y. , Amin, A. , Yang, C. - K. K. , and Marković, D. , Scalability And Design-space Analysis of A 1T-1MTJ Memory Cell, Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH). IEEE, pp. 32-36, 2011. (1.1 MB)
R. Dorrance, Ren, F. , and Marković, D. , A Scalable Sparse Matrix-vector Multiplication Kernel for Energy-efficient Sparse-BLAS on FPGAs, Proceedings of the 2014 ACM/SIGDA International Symposium on Field-programmable Gate Arrays (FPGA). ACM, pp. 161-170, 2014. (558.35 KB)
R. Dorrance, Ren, F. , Toriyama, Y. , Hafez, A. Amin, Yang, C. - K. K. , and Marković, D. , Scalability and Design-space Analysis of A 1T-1MTJ Memory Cell For STT-RAMs, IEEE Transactions on Electron Devices, vol. 59, no. 4, pp. 878–887, 2012. (1.1 MB)
C
L. Cheng, Xu, W. , Ren, F. , Gong, F. , Gupta, P. , and He, L. , Statistical Timing and Power Analysis of VLSI Considering Non-linear Dependence, the VLSI Journal Integration, vol. 47, no. 4, pp. 487–498, 2014. (845.26 KB)
B
S. Biookaghazadeh, Zhao, M. , and Ren, F. , Are FPGAs Suitable for Edge Computing?, The USENIX Workshop on Hot Topics in Edge Computing (HotEdge '18). BOSTON, MA, 2018. (363.22 KB)
E. Bank-Tavakoli, Riera, M. , Quraishi, M. Hassan, and Ren, F. , FSCHOL: An OpenCL-based HPC Framework for Accelerating Sparse Cholesky Factorization on FPGAs, The 33rd International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD). Virtual Event, pp. 209-220, 2021. (380.33 KB)

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