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2012
R. Dorrance, Ren, F. , Toriyama, Y. , Hafez, A. Amin, Yang, C. - K. K. , and Marković, D. , Scalability and Design-space Analysis of A 1T-1MTJ Memory Cell For STT-RAMs, IEEE Transactions on Electron Devices, vol. 59, no. 4, pp. 878–887, 2012. (1.1 MB)
2011
H. Park, Dorrance, R. , Amin, A. , Ren, F. , Marković, D. , and Yang, C. K. Ken, Analysis of STT-RAM Cell Design With Multiple MTJs Per Access, Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH). IEEE Computer Society, pp. 53-58, 2011. (320.88 KB)
F. Ren, Energy-performance Characterization of CMOS/Magnetic Tunnel Junction (MTJ) Hybrid Logic Circuits, University of California, Los Angeles, Los Angeles, 2011. (1.05 MB)
R. Dorrance, Ren, F. , Toriyama, Y. , Amin, A. , Yang, C. - K. K. , and Marković, D. , Scalability And Design-space Analysis of A 1T-1MTJ Memory Cell, Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH). IEEE, pp. 32-36, 2011. (1.1 MB)
2010
F. Ren and Marković, D. , True Energy-performance Analysis Of The MTJ-based Logic-in-memory Architecture (1-bit Full Adder), IEEE Transactions on Electron Devices, vol. 57, no. 5, pp. 1023–1028, 2010. (632.59 KB)

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