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M. Riera, Bank-Tavakoli, E. , Quraishi, M. Hassan, and Ren, F. , HALO 1.0: A Hardware-agnostic Accelerator Orchestration Framework for Enabling Hardware-agnostic Programming with True Performance Portability for Heterogeneous HPC, International Conference on Supercomputing (ICS). Under Review.
F. Ren and Marković, D. , A Configurable 12-to-237KS/s 12.8 mW Sparse-approximation Engine for Mobile ExG Data Aggregation, Proceedings of the 2015 IEEE International Solid-State Circuits Conference (ISSCC). IEEE, pp. 68-78, 2015. (6.94 MB)
F. Ren and Marković, D. , True Energy-performance Analysis Of The MTJ-based Logic-in-memory Architecture (1-bit Full Adder), IEEE Transactions on Electron Devices, vol. 57, no. 5, pp. 1023–1028, 2010. (632.59 KB)
F. Ren and Marković, D. , A Configurable 12–237 kS/s 12.8 mW Sparse-Approximation Engine for Mobile Data Aggregation of Compressively Sampled Physiological Signals, IEEE Journal of Solid-State Circuits, vol. 51, no. 1, pp. 68-78, 2016. (3.07 MB)
F. Ren, Dorrace, R. , Xu, W. , and Marković, D. , A Single-precision Compressive Sensing Signal Reconstruction Engine on FPGAs, Proceedings of the 23rd International Conference on Field Programmable Logic and Applications (FPL). IEEE, pp. 1-4, 2013. (358.12 KB)
F. Ren, A Scalable VLSI Architecture for Real-Time and Energy-Efficient Sparse Approximation in Compressive Sensing Systems, University of California, Los Angeles, Los Angeles, 2015. (5.71 MB)
F. Ren, Zhang, C. , Liu, L. , Xu, W. , Owall, V. , and Marković, D. , A Square-Root-Free Matrix Decomposition Method for Energy-Efficient Least Square Computation on Embedded Systems, IEEE Embedded Systems Letters, vol. 6, no. 4, pp. 73–76, 2014. (912.74 KB)
F. Ren, Xu, K. , and Zhang, Z. , LAPRAN: A SCALABLE LAPLACIAN PYRAMID RECONSTRUCTIVE ADVERSARIAL NETWORK FOR FLEXIBLE COMPRESSIVE SENSING RECONSTRUCTION, 16/745,817, 2020.
F. Ren, Energy-performance Characterization of CMOS/Magnetic Tunnel Junction (MTJ) Hybrid Logic Circuits, University of California, Los Angeles, Los Angeles, 2011. (1.05 MB)
F. Ren, Xu, W. , and Marković, D. , Scalable and Parameterised VLSI Architecture for Efficient Sparse Approximation in FPGAs And SoCs, IET Electronics Letters, vol. 49, no. 23, pp. 1440–1441, 2013. (154.45 KB)
F. Ren, Park, H. , Dorrance, R. , Toriyama, Y. , Yang, C. - K. K. , and Marković, D. , A Body-voltage-sensing-based Short Pulse Reading Circuit for Spin-torque Transfer RAMs (STT-RAMs), Proceedings of the 2012 13th International Symposium on Quality Electronic Design (ISQED). IEEE, pp. 275-282, 2012. (559.47 KB)
F. Ren, Park, H. , Yang, C. - K. K. , and Marković, D. , Reference Calibration of Body-voltage Sensing Circuit for High-speed STT-RAMs, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 60, no. 11, pp. 2932–2939, 2013. (1.78 MB)
F. Ren and Xu, K. , Real time end-to-end learning system for a high frame rate video compressive sensing network, US16/165,568, 2019.