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A. Dua, Hardware Acceleration of Video Analytics on FPGA Using OpenCL, Arizona State University, Tempe, 2019. (2.83 MB)
A. Dua, Li, Y. I. , and Ren, F. , Systolic-CNN: An OpenCL-defined Scalable Run-time-flexible FPGA Accelerator Architecture for Accelerating Convolutional Neural Network Inference in Cloud/Edge Computing, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Under Review.
R. Dorrance, Ren, F. , Toriyama, Y. , Hafez, A. Amin, Yang, C. - K. K. , and Marković, D. , Scalability and Design-space Analysis of A 1T-1MTJ Memory Cell For STT-RAMs, IEEE Transactions on Electron Devices, vol. 59, no. 4, pp. 878–887, 2012. (1.1 MB)
R. Dorrance, Ren, F. , Toriyama, Y. , Amin, A. , Yang, C. - K. K. , and Marković, D. , Scalability And Design-space Analysis of A 1T-1MTJ Memory Cell, Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH). IEEE, pp. 32-36, 2011. (1.1 MB)
R. Dorrance, Ren, F. , and Marković, D. , A Scalable Sparse Matrix-vector Multiplication Kernel for Energy-efficient Sparse-BLAS on FPGAs, Proceedings of the 2014 ACM/SIGDA International Symposium on Field-programmable Gate Arrays (FPGA). ACM, pp. 161-170, 2014. (558.35 KB)