@inproceedings {London, UK, title = {STPLS3D: A Large-Scale Synthetic and Real Aerial Photogrammetry 3D Point Cloud Dataset}, year = {2022}, month = {11/2022}, address = {London, UK}, abstract = {

Although various 3D datasets with different functions and scales have been proposed recently, it remains challenging for individuals to complete the whole pipeline of large- scale data collection, sanitization, and annotation. Moreover, the created datasets usually face the challenge of extremely imbalanced class distribution or partial low-quality data samples. Motivated by this, we explore the procedurally synthetic 3D data generation paradigm to equip individuals with the full capability of creating large-scale annotated photogrammetry point clouds. Specifically, we introduce a synthetic aerial photogrammetry point clouds generation pipeline that takes full advantage of open geospatial data sources and off-the-shelf commercial packages. Unlike generating synthetic data in virtual games, where the simulated data usually have limited gaming environments created by artists, the proposed pipeline simulates the reconstruction process of the real environment by following the same UAV flight pattern on different synthetic terrain shapes and building densities, which ensure similar quality, noise pattern, and diversity with real data. In addition, the precise semantic and instance annotations can be generated fully automatically, avoiding the expensive and time-consuming manual annotation. Based on\ the proposed pipeline, we present a richly-annotated synthetic 3D aerial photogrammetry point cloud dataset, termed STPLS3D, with more than 16 km2 of landscapes and up to 18 fine-grained semantic categories. For verification purposes, we also provide datasets collected from four areas in the real environment. Extensive experiments conducted on our datasets demonstrate the effectiveness and quality of the proposed synthetic dataset.

}, keywords = {psclab}, url = {https://www.stpls3d.com/}, author = {Meida Chen and Qingyong Hu and Zifan Yu and Hugues Thomas and Andrew Feng and Yu Hou and Kyle McCullough and Fengbo Ren and Lucio Soibelman} } @article {498, title = {A Survey of System Architectures and Techniques for FPGA Virtualization}, journal = { IEEE Transactions on Parallel and Distributed Systems}, volume = {32}, year = {2021}, month = {09/2021}, pages = {2216-2230}, abstract = {

FPGA accelerators are gaining increasing attention in both cloud and edge computing because of their hardware flexibility, high computational throughput, and low power consumption. However, the design flow of FPGAs often requires specific knowledge of the underlying hardware, which hinders the wide adoption of FPGAs by application developers. Therefore, the virtualization of FPGAs becomes extremely important to create a useful abstraction of the hardware suitable for application developers. Such abstraction also enables the sharing of FPGA resources among multiple users and accelerator applications, which is important because, traditionally, FPGAs have been mostly used in single-user, single-embedded-application scenarios. There are many works in the field of FPGA virtualization covering different aspects and targeting different application areas. In this survey, we review the system architectures used in the literature for FPGA virtualization. In addition, we identify the primary objectives of FPGA virtualization, based on which we summarize the techniques for realizing FPGA virtualization. This survey helps researchers to efficiently learn about FPGA virtualization research by providing a comprehensive review of the existing literature.

}, keywords = {psclab}, issn = {1045-9219}, doi = {10.1109/TPDS.2021.3063670}, author = {Masudul Hassan Quraishi and Erfan Bank-Tavakoli and Fengbo Ren} } @article {499, title = {Systolic-CNN: An OpenCL-defined Scalable Run-time-flexible FPGA Accelerator Architecture for Accelerating Convolutional Neural Network Inference in Cloud/Edge Computing}, year = {2020}, month = {12/2020}, abstract = {

This paper presents Systolic-CNN, an OpenCL-defined scalable, runtime-flexible FPGA accelerator architecture, optimized for accelerating the inference of various convolutional neural networks (CNNs) in multi-tenancy cloud/edge computing. The existing OpenCL-defined FPGA accelerators for CNN inference are insufficient due to limited flexibility for supporting multiple CNN models at run time and poor scalability resulting in underutilized FPGA resources and limited computational parallelism. Systolic-CNN adopts a highly pipelined and paralleled 1-D systolic array architecture, which efficiently explores both spatial and temporal parallelism for accelerating CNN inference on FPGAs. Systolic-CNN is highly scalable and parameterized, which can be easily adapted by users to achieve up to 100\% utilization of the coarse-grained computation resources (i.e., DSP blocks) for a given FPGA. Systolic-CNN is also run-time-flexible in the context of multi-tenancy cloud/edge computing, which can be time-shared to accelerate a variety of CNN models at run time without the need of recompiling the FPGA kernel hardware nor reprogramming the FPGA. The experiment results based on an Intel Arria/Stratix 10 GX FPGA Development board show that the optimized single-precision implementation of Systolic-CNN can achieve an average inference latency of 7ms/2ms, 84ms/33ms, 202ms/73ms, 1615ms/873ms, and 900ms/498ms per image for accelerating AlexNet, ResNet-50, ResNet-152, RetinaNet, and Light-weight RetinaNet, respectively. Codes are available at https://github.com/PSCLab-ASU/Systolic-CNN.

}, keywords = {psclab}, url = {https://arxiv.org/pdf/2012.03177.pdf}, author = {Akshay Dua and YIxing Li and Fengbo Ren} } @inproceedings {Orleans, Louisana, title = {SqueezedText: A Real-time Scene Text Recognition by Binary Convolutional Encoder-decoder Network}, year = {2018}, month = {04/2018}, pages = {7194-7201}, address = {New Orleans, Louisana}, abstract = {

A new approach for real-time scene text recognition is proposed in this paper. A novel binary convolutional encoderdecoder network (B-CEDNet) together with a bidirectional recurrent neural network (Bi-RNN). The B-CEDNet is engaged as a visual front-end to provide elaborated character detection, and a back-end Bi-RNN performs characterlevel sequential correction and classification based on learned contextual knowledge. The front-end B-CEDNet can process multiple regions containing characters using a one-off forward operation, and is trained under binary constraints with significant compression. Hence it leads to both remarkable inference run-time speedup as well as memory usage reduction. With the elaborated character detection, the back-end Bi-RNN merely processes a low dimension feature sequence with category and spatial information of extracted characters for sequence correction and classification. By training with over 1,000,000 synthetic scene text images, the B-CEDNet achieves a recall rate of 0.86, precision of 0.88 and F-score of 0.87 on ICDAR-03 and ICDAR-13. With the correction and classification by Bi-RNN, the proposed real-time scene text recognition achieves state-of-the-art accuracy while only consumes less than 1-ms inference run-time. The flow processing flow is realized on GPU with a small network size of 1.01 MB for B-CEDNet and 3.23 MB for Bi-RNN, which is much faster and smaller than the existing solutions.

}, keywords = {psclab}, author = {Zichuan Liu and YIxing Li and Fengbo Ren and Hao Yu and Wangling Goh} } @article {33, title = {Scalable and Parameterized VLSI Architecture for Compressive Sensing Sparse Approximation}, number = {US14/446,272}, year = {2015}, month = {Jan 29, 2015}, abstract = {

Systems and methods for implementing a scalable very-large-scale integration (VLSI) architecture to perform compressive sensing (CS) hardware reconstruction for data signals in accordance with embodiments of the invention are disclosed. The VLSI architecture is optimized for CS signal reconstruction by implementing a reformulation of the orthogonal matching pursuit (OMP) process and utilizing architecture resource sharing techniques. Typically, the VLSI architecture is a CS reconstruction engine that includes a vector and scalar computation cores where the cores can be time-multiplexed (via dynamic configuration) to perform each task associated with OMP. The vector core includes configurable processing elements (PEs) connected in parallel. Further, the cores can be linked by data-path memories, where complex data flow of OMP can be customized utilizing local memory controllers synchronized by a top-level finite-state machine. The computing resources (cores and data-paths) can be reused across the entire OMP process resulting in optimal utilization of the PEs.

}, keywords = {psclab}, issn = {US10073701B2}, url = {https://www.google.com/patents/US20150032990}, author = {Dejan Markovic and Fengbo Ren} } @mastersthesis {35, title = {A Scalable VLSI Architecture for Real-Time and Energy-Efficient Sparse Approximation in Compressive Sensing Systems}, volume = {Doctor of Philosophy}, year = {2015}, month = {Jan.}, school = {University of California, Los Angeles}, type = {Ph.D. Dissertation}, address = {Los Angeles}, abstract = {

Digital electronic industry today relies on Nyquist sampling theorem, which requires to double the size (sampling rate) of the signal representation on the Fourier basis to avoid information loss. However, most natural signals have very sparse representations on some other orthogonal (non-Fourier) basis. This mismatch implies a large redundancy in Nyquist-sampled data, making compression a necessity prior to storage or transmission. Recent advances in compressive sensing (CS) theory offer us an alternative data acquisition framework, which can greatly impact power-starved applications such as wireless sensors. CS techniques provide a universal approach to sample compressible signals at a rate significantly below the Nyquist rate with limited information loss. Therefore, CS is a promising technology for realizing configurable, cost-effective, miniaturized, and ultra-low-power data acquisition devices for mobile and wearable applications. However, the digital signal processing of compressively-sampled data involves solving a sparse approximation problem, which requires iterative-searching algorithms that have high computational complexity and require intensive memory access. As a result, existing software solutions are neither energy-efficient nor cost-effective for real-time processing of compressively-sampled data, especially when the processing is to be performed on energy-limited devices. To solve this problem, this dissertation presents a scalable VLSI architecture that can be implemented on field-programmable gate arrays (FPGAs) or system-on-chips (SoCs) to perform dedicated-hardware-driven sparse approximation. A VLSI soft-IP core of the sparse approximation engine is developed in Verilog-HDL, which supports a floating-point data format with 10 design parameters, providing a high dynamic range and the flexibility for application-specific user customizations. Taking advantage of the algorithm-architecture co-design that leverages algorithm reformulations, configurable architectures, and efficient memory mapping schemes, the proposed VLSI architecture features a 100\% utilization of the computing resources and is scalable in terms of computation parallelism and memory capability. The hardware emulation of the soft-IP core on a 28-nm Xilinx Kintex-7 FPGA shows that our design achieves the same level of accuracy as the double-precision C program running on an Intel Core i7-4700MQ mobile processor, while providing 47\–147x speed-up for ECG signal reconstruction. Furthermore, a 12\–237 KS/s 12.8 mW sparse approximation engine chip is realized in a 40-nm CMOS technology for enabling the mobile data aggregation of compressively sampled biomedical signals in CS-based wireless health monitoring systems. The measurement results show that the sparse approximation engine chip operating at the minimum energy point achieves a real-time throughput for reconstructing 61\–237 channels of biomedical signals simultaneously with \<1\% of a mobile device\&$\#$39;s 2W power budget, which is 14,100x more energy-efficient than the software solver running on the CPU. For high-sparsity signal reconstruction, the sparse approximation engine chip is 76\–350x more energy-efficient than prior hardware designs. With a \<1\% power budget of a mobile device, the 5.13 mm2 sparse approximation engine chip integrated in 40-nm CMOS can enable a 2\–3x energy saving at CS-based sensor nodes while providing timely feedback and bringing signal intelligence closer to the user, presenting a significant advantage for 24/7 wireless health monitoring.

}, keywords = {psclab}, author = {Ren, Fengbo} } @inproceedings {23, title = {A Scalable Sparse Matrix-vector Multiplication Kernel for Energy-efficient Sparse-BLAS on FPGAs}, year = {2014}, month = {02/2014}, pages = {161-170}, publisher = {ACM}, abstract = {

Sparse Matrix-Vector Multiplication (SpMxV) is a widely used mathematical operation in many high-performance scientific and engineering applications. In recent years, tuned software libraries for multi-core microprocessors (CPUs) and graphics processing units (GPUs) have become the status quo for computing SpMxV. However, the computational throughput of these libraries for sparse matrices tends to be significantly lower than that of dense matrices, mostly due to the fact that the compression formats required to efficiently store sparse matrices mismatches traditional computing architectures. This paper describes an FPGA-based SpMxV kernel that is scalable to efficiently utilize the available memory bandwidth and computing resources. Benchmarking on a Virtex-5 SX95T FPGA demonstrates an average computational efficiency of 91.85\%. The kernel achieves a peak computational efficiency of 99.8\%, a \>50x improvement over two Intel Core i7 processors (i7-2600 and i7-4770) and showing a \>300x improvement over two NVIDA GPUs (GTX 660 and GTX Titan), when running the MKL and cuSPARSE sparse-BLAS libraries, respectively. In addition, the SpMxV FPGA kernel is able to achieve higher performance than its CPU and GPU counterparts, while using only 64 single-precision processing elements, with an overall 38-50x improvement in energy efficiency.

}, keywords = {psclab}, url = {http://dl.acm.org/citation.cfm?id=2554785}, author = {Dorrance, Richard and Ren, Fengbo and Markovi{\'c}, Dejan} } @article {22, title = {A Square-Root-Free Matrix Decomposition Method for Energy-Efficient Least Square Computation on Embedded Systems}, journal = {IEEE Embedded Systems Letters}, volume = {6}, year = {2014}, month = {Aug.}, pages = {73{\textendash}76}, abstract = {

QR decomposition (QRD) is used to solve least-squares (LS) problems for a wide range of applications. However, traditional QR decomposition methods, such as Gram-Schmidt (GS), require high computational complexity and nonlinear operations to achieve high throughput, limiting their usage on resource-limited platforms. To enable efficient LS computation on embedded systems for real-time applications, this paper presents an alternative decomposition method, called QDRD, which relaxes system requirements while maintaining the same level of performance. Specifically, QDRD eliminates both the square-root operations in the normalization step and the divisions in the subsequent backward substitution. Simulation results show that the accuracy and reliability of factorization matrices can be significantly improved by QDRD, especially when executed on precision-limited platforms. Furthermore, benchmarking results on an embedded platform show that QDRD provides constantly better energy-efficiency and higher throughput than GS-QRD in solving LS problems. Up to 4 and 6.5 times improvement in energy-efficiency and throughput, respectively, can be achieved for small-size problems.

}, keywords = {psclab}, url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6882128}, author = {Ren, Fengbo and Zhang, Chenxin and Liu, Liang and Xu, Wenyao and Owall, V and Markovi{\'c}, Dejan} } @article {17, title = {Statistical Timing and Power Analysis of VLSI Considering Non-linear Dependence}, journal = {the VLSI Journal Integration}, volume = {47}, year = {2014}, month = {Sep.}, pages = {487{\textendash}498}, abstract = {

Majority of practical multivariate statistical analysis and optimizations model interdependence among random variables in terms of the linear correlation. Though linear correlation is simple to use and evaluate, in several cases non-linear dependence between random variables may be too strong to ignore. In this paper, we propose polynomial correlation coefficients as simple measure of multi-variable non-linear dependence and show that the need for modeling non-linear dependence strongly depends on the end function that is to be evaluated from the random variables. Then, we calculate the errors in estimation resulting from assuming independence of components generated by linear de-correlation techniques, such as PCA and ICA. The experimental results show that the error predicted by our method is within 1\% error compared to the real simulation of statistical timing and leakage analysis. In order to deal with non-linear dependence, we further develop a target-function-driven component analysis algorithm (FCA) to minimize the error caused by ignoring high order dependence. We apply FCA to statistical leakage power analysis and SRAM cell noise margin variation analysis. Experimental results show that the proposed FCA method is more accurate compared to the traditional PCA or ICA.

}, keywords = {psclab}, url = {http://www.sciencedirect.com/science/article/pii/S0167926014000029}, author = {Cheng, Lerong and Xu, Wenyao and Ren, Fengbo and Gong, Fang and Gupta, Puneet and He, Lei} } @article {21, title = {Scalable and Parameterised VLSI Architecture for Efficient Sparse Approximation in FPGAs And SoCs}, journal = {IET Electronics Letters}, volume = {49}, year = {2013}, month = {Nov.}, pages = {1440{\textendash}1441}, abstract = {

A parameterised and scalable very large scale integration (VLSI) soft intellectual property (IP) is presented that can be implemented in programmable logic devices, such as field programmable gate arrays (FPGAs) or a system-on-chip design for efficient sparse approximation. The proposed architecture is optimised based on the orthogonal matching pursuit algorithm by both algorithm reformulation and architecture resource sharing techniques. The soft IP core supports a floating-point data format with 10 design parameters, which provides the necessary flexibility for application-specific customisation. The soft IP is evaluated on various FPGA platforms. The evaluation results show that design can achieve up to 30\% higher throughput than the existing solutions while offering a larger dynamic range capability and better design flexibility.

}, keywords = {psclab}, url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6675715}, author = {Ren, Fengbo and Xu, Wenyao and Markovi{\'c}, Dejan} } @inproceedings {31, title = {See UV on Your Skin: An Ultraviolet Sensing and Visualization System}, year = {2013}, month = {09/2013}, pages = {22-28}, publisher = {ICST (Institute for Computer Sciences, Social-Informatics and Telecommunications Engineering)}, abstract = {

These days, as the Earth{\textquoteright}s protective ozone layer gets thinner, ultraviolet (UV) radiation threat is growing. In addition, getting tanned as a fashion leads people to wear less clothing, which increases UV intake. Excessive exposure to ultraviolet will lead to sunburn and even skin cancer. Therefore, neither insufficient nor excessive exposure is desirable. Although there are tons of UV meters on the market, a user may have a hard time to understand the unintuitive UV index reading. Thus, there is a potential demand for a portable system which can keep track of daily UV exposure dose, visualize possible sunburned consequences, and provide appropriate skin care recommendations. In this paper, we present a personalized UV monitoring and notification system. This system can continuously track UV exposure by wearable UV sensors. It can also visualize the cumulative UV exposure dose according to a predictive sunburned skin color model. Such an augmented skin color can provide a warning message to indicate the possible result of continuous UV exposure. Compared with other existing systems, our solution not only allows users to monitor their daily UV exposure, but also provides an unobtrusive UV visualization model which effectively warns users to take appropriate actions to avoid potential skin damage. The system has been tested on 9 subjects, and the evaluation feedback indicates that our system is promising for UV monitoring and sunburn prevention.

}, keywords = {psclab}, url = {http://dl.acm.org/citation.cfm?id=2555324}, author = {Zhang, Xiaoyi and Xu, Wenyao and Huang, Ming-Chun and Amini, Navid and Ren, Fengbo} } @inproceedings {26, title = {A Single-precision Compressive Sensing Signal Reconstruction Engine on FPGAs}, year = {2013}, month = {09/2013}, pages = {1-4}, publisher = {IEEE}, abstract = {

Compressive sensing (CS) is a promising technology for the low-power and cost-effective data acquisition in wireless healthcare systems. However, its efficient realtime signal reconstruction is still challenging, and there is a clear demand for hardware acceleration. In this paper, we present the first single-precision floating-point CS reconstruction engine implemented a Kintex-7 FPGA using the orthogonal matching pursuit (OMP) algorithm. In order to achieve high performance with maximum hardware utilization, we propose a highly parallel architecture that shares the computing resources among different tasks of OMP by using configurable processing elements (PEs). By fully utilizing the FPGA recourses, our implementation has 128 PEs in parallel and operates at 53.7 MHz. In addition, it can support 2x larger problem size and 10x more sparse coefficients than prior work, which enables higher reconstruction accuracy by adding finer details to the recovered signal. Hardware results from the ECG reconstruction tests show the same level of accuracy as the double-precision C program. Compared to the execution time of a 2.27 GHz CPU, the FPGA reconstruction achieves an average speed-up of 41x.

}, keywords = {psclab}, url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6645574}, author = {Ren, Fengbo and Dorrace, Richard and Xu, Wenyao and Markovi{\'c}, Dejan} } @article {18, title = {Scalability and Design-space Analysis of A 1T-1MTJ Memory Cell For STT-RAMs}, journal = {IEEE Transactions on Electron Devices}, volume = {59}, year = {2012}, month = {Jan.}, pages = {878{\textendash}887}, abstract = {

We present a design-space feasibility region, as a function of magnetic tunnel junction (MTJ) characteristics and target memory specifications, to explore the design margin of a one-transistor-one-magnetic-tunnel-junction (1T-1MTJ) memory cell for spin-transfer torque random access memories (STT-RAMs). Data from measured devices are used to model the statistical variation of an MTJ{\textquoteright}s critical switching current and resistance. The sensitivity of the design space to different design parameters is also analyzed for the scaling of both the MTJ and the underlying transistor technology. A design flow, using a sensitivity-based analysis and an MTJ switching model based on the Landau-Lifshitz-Gilbert equation, is proposed to optimize design margins for gigabit-scale memories. Design points for improved yield, density, and memory performance are extracted from MTJ-compatible complementary metal-oxide-semiconductor (CMOS) technologies for 90-, 65-, 45-, and 32-nm processes. Predictive technology models are used to explore the future scalability of STT-RAMs in upcoming 22- and 16-nm technology nodes. Our analysis shows that, to achieve Flash-like densities ( \<; 6F2) in advanced CMOS technologies, aggressive scaling of the critical switching current density will be required.

}, keywords = {psclab}, url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6140952}, author = {Dorrance, Richard and Ren, Fengbo and Toriyama, Yuta and Hafez, Amr Amin and Yang, C-KK and Markovi{\'c}, Dejan} } @inproceedings {24, title = {Scalability And Design-space Analysis of A 1T-1MTJ Memory Cell}, year = {2011}, month = {01/2011}, pages = {32-36}, publisher = {IEEE}, abstract = {

This paper introduces a design-space feasibility region as a function of MTJ characteristics and memory target specifications. The sensitivity of the design space is analyzed for scaling of both MTJ and underlying transistor technology. Design points for improved yield, density, and memory performance can be extracted for 90nm down to 32nm processes based on measured MTJ devices. To achieve flash-like densities in upcoming 22nm and 16nm technology nodes, scaling of the critical switching current density is required.

}, keywords = {psclab}, url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5941480}, author = {Dorrance, Richard and Ren, Fengbo and Toriyama, Yuta and Amin, Amr and Yang, C-KK and Markovi{\'c}, Dejan} }