@inproceedings {Virtual Event, title = {FSCHOL: An OpenCL-based HPC Framework for Accelerating Sparse Cholesky Factorization on FPGAs}, year = {2021}, month = {10/2021}, pages = {209-220}, address = {Virtual Event}, abstract = {

The proposed FSCHOL framework consists of an FPGA kernel implementing a throughput-optimized hardware architecture for accelerating the supernodal multifrontal algorithm for sparse Cholesky factorization and a host program implementing a novel scheduling algorithm for finding the optimal execution order of supernodes computations for an elimination tree on the FPGA to eliminate the need for off-chip memory access for storing intermediate results. Moreover, the proposed scheduling algorithm minimizes on-chip memory requirements for buffering intermediate results by resolving the dependency of parent nodes in an elimination tree through temporal parallelism. Experiment results for factorizing a set of sparse matrices in various sizes from SuiteSparse Matrix Collection show that the proposed FSCHOL implemented on an Intel Stratix 10 GX FPGA development board achieves on average 5.5\× and 9.7\× higher performance and 10.3\× and 24.7\× lower energy consumption than implementations of CHOLMOD on an Intel Xeon E5-2637 CPU and an NVIDIA V100 GPU, respectively.

}, keywords = {psclab}, doi = {10.1109/SBAC-PAD53543.2021.00032}, author = {Erfan Bank-Tavakoli and Michael Riera and Masudul Hassan Quraishi and Fengbo Ren} }