@inproceedings {Rhodes Island, Greece, title = {Automatic Error Detection in Integrated Circuits Image Segmentation: A Data-driven Approach}, year = {2023}, month = {06/2023}, address = {Rhodes Island, Greece}, keywords = {psclab}, author = {Zhikang Zhang and Bruno Machado Trindade and Michael Green and Zifan Yu and Christopher Pawlowicz and Fengbo Ren} } @inproceedings {Rhodes Island, Greece, title = {Enhanced Low-resolution LiDAR-Camera Calibration Via Depth Interpolation and Supervised Contrastive Learning}, year = {2023}, month = {06/2023}, address = {Rhodes Island, Greece}, keywords = {psclab}, author = {Zhikang Zhang and Zifan Yu and Suya You and Raghuveer Rao and Sanjeev Agarwal and Fengbo Ren} } @inproceedings {Bordeaux, France, title = {A Data-Driven Approach for Automated Integrated Circuit Segmentation of Scan Electron Microscopy Images}, year = {2022}, month = {10/2022}, address = {Bordeaux, France}, abstract = {

This paper proposes an automated data-driven integrated
circuit segmentation approach of scan electron microscopy
(SEM) images inspired by state-of-the-art CNN-based image
perception methods. Based on the requirements derived from
real industry applications, we take wire segmentation and via
detection algorithms to generate integrated circuit segmentation
maps from SEMs in our approach. On SEM images
collected in the industrial applications, our method achieves
an average of 50.71 on Electrically Significant Difference
(ESD) in the wire segmentation task and 99.05\% F1 score
in the via detection task, which achieves about 85\% and 8\%
improvements over the reference method, respectively.

}, keywords = {psclab}, author = {Zifan Yu and Bruno Machado Trindade and Michael Green and Zhikang Zhang and Pullela Sneha and Bank-Tavakoli, Erfan and Christopher Pawlowicz and Ren, Fengbo} } @inproceedings {London, UK, title = {STPLS3D: A Large-Scale Synthetic and Real Aerial Photogrammetry 3D Point Cloud Dataset}, year = {2022}, month = {11/2022}, address = {London, UK}, abstract = {

Although various 3D datasets with different functions and scales have been proposed recently, it remains challenging for individuals to complete the whole pipeline of large- scale data collection, sanitization, and annotation. Moreover, the created datasets usually face the challenge of extremely imbalanced class distribution or partial low-quality data samples. Motivated by this, we explore the procedurally synthetic 3D data generation paradigm to equip individuals with the full capability of creating large-scale annotated photogrammetry point clouds. Specifically, we introduce a synthetic aerial photogrammetry point clouds generation pipeline that takes full advantage of open geospatial data sources and off-the-shelf commercial packages. Unlike generating synthetic data in virtual games, where the simulated data usually have limited gaming environments created by artists, the proposed pipeline simulates the reconstruction process of the real environment by following the same UAV flight pattern on different synthetic terrain shapes and building densities, which ensure similar quality, noise pattern, and diversity with real data. In addition, the precise semantic and instance annotations can be generated fully automatically, avoiding the expensive and time-consuming manual annotation. Based on\ the proposed pipeline, we present a richly-annotated synthetic 3D aerial photogrammetry point cloud dataset, termed STPLS3D, with more than 16 km2 of landscapes and up to 18 fine-grained semantic categories. For verification purposes, we also provide datasets collected from four areas in the real environment. Extensive experiments conducted on our datasets demonstrate the effectiveness and quality of the proposed synthetic dataset.

}, keywords = {psclab}, url = {https://www.stpls3d.com/}, author = {Meida Chen and Qingyong Hu and Zifan Yu and Hugues Thomas and Andrew Feng and Yu Hou and Kyle McCullough and Fengbo Ren and Lucio Soibelman} } @article {379, title = {A 34-FPS 698-GOP/s/W Binarized Deep Neural Network-based Natural Scene Text Interpretation Accelerator for Mobile Edge Computing}, journal = {IEEE Transactions on Industrial Electronics (TIE)}, volume = {66}, year = {2019}, month = {10/2018}, pages = {7407-7416}, abstract = {

The scene text interpretation is a critical part of natural scene interpretation. Currently, most of the existing work is based on high-end GPU implementation, which is commonly used on the server side. However, in IoT application scenarios, the communication overhead from the edge device to the server is quite large, which sometimes even dominates the total processing time. Hence, the edgecomputing oriented design is needed to solve this problem. In this paper, we present an architectural design and implementation of a natural scene text interpretation (NSTI) accelerator, which can classify and localize the text region on pixel-level efficiently in real-time on mobile devices. To target the real-time and low-latency processing, the Binary Convolutional Encoder-decoder Network (B-CEDNet) is adopted as the core architecture to enable massive parallelism due to its binary feature. Massively parallelized computations and a highly pipelined data flow control enhance its latency and throughput performance. In addition, all the binarized intermediate results and parameters are stored on chip to eliminate the power consumption and latency overhead of the off-chip communication. The NSTI accelerator is implemented in a 40nm CMOS technology, which can process scene text images (size of 128x32) at 34 fps and latency of 40 ms for pixelwise interpretation with the pixelwise classification accuracy over 90\% on ICDAR- 03 and ICDAR-13 dataset. The real energy-efficiency is 698 GOP/s/W and the peak energy-efficiency can get up to 7825 GOP/s/W. The proposed accelerator is 7 more energy efficient than its optimized GPU-based implementation counterpart, while maintaining a real-time throughput with latency of 40 ms.

}, keywords = {psclab}, doi = {10.1109/TIE.2018.2875643}, url = {https://ieeexplore.ieee.org/document/8513982}, author = {YIxing Li and Zichuan Liu and Wenye Liu and Yu Jiang and Yongliang Wang and Wang Ling Goh and Hao Yu and Fengbo Ren} } @article {366, title = {A Deep Learning Approach for Targeted Contrast-Enhanced Ultrasound Based Prostate Cancer Detection}, journal = {IEEE/ACM Transactions on Computational Biology and Bioinformatics}, volume = {16}, year = {2019}, month = {05/2018}, pages = {1794-1801}, abstract = {

The important role of angiogenesis in cancer development has driven many researchers to investigate the prospects of noninvasive cancer diagnosis based on the technology of contrast-enhanced ultrasound (CEUS) imaging. This paper presents a deep learning framework to detect prostate cancer in the sequential CEUS images. The proposed method uniformly extracts features from both the spatial and the temporal dimensions by performing three-dimensional convolution operations, which captures the dynamic information of the perfusion process encoded in multiple adjacent frames for prostate cancer detection. The deep learning models were trained and validated against expert delineations over the CEUS images recorded using two types of contrast agents, i.e. the anti-PSMA based agent targeted to prostate cancer cells and the non-targeted blank agent. Experiments showed that the deep learning method achieved over 91\% specificity and 90\% average accuracy over the targeted CEUS images for prostate cancer detection, which was superior (p \< 0.05) than previously reported approaches and implementations.

}, keywords = {psclab}, doi = {10.1109/TCBB.2018.2835444}, url = {https://ieeexplore.ieee.org/document/8357938}, author = {Yujie Feng and Fan Yang and Xichuan Zhou and Yanli Guo and Fang Tang and Fengbo Ren and Jishun Guo and Shuiwang Ji} } @article {369, title = {A GPU-Outperforming FPGA Accelerator Architecture for Binary Convolutional Neural Networks}, journal = {ACM Journal on Emerging Technologies in Computing (JETC) - Special Issue on Frontiers of Hardware and Algorithms for On-chip Learning​}, volume = {14}, year = {2018}, month = {07/2018}, pages = {18.16}, chapter = {18.1}, abstract = {

FPGA-based hardware accelerators for convolutional neural networks (CNNs) have obtained great attentions due to their higher energy efficiency than GPUs. However, it is challenging for FPGA-based solutions to achieve a higher throughput than GPU counterparts. In this paper, we demonstrate that FPGA acceleration can be a superior solution in terms of both throughput and energy efficiency when a CNN is trained with binary constraints on weights and activations. Specifically, we propose an optimized FPGA accelerator architecture tailored for bitwise convolution and normalization that features massive spatial parallelism with deep pipelines stages. A key advantage of the FPGA accelerator is that its performance is insensitive to data batch size, while the performance of GPU acceleration varies largely depending on the batch size of the data. Experiment results show that the proposed accelerator architecture for binary CNNs running on a Virtex-7 FPGA is 8.3x faster and 75x more energy-efficient than a Titan X GPU for processing online individual requests in small batch sizes. For processing static data in large batch sizes, the proposed solution is on a par with a Titan X GPU in terms of throughput while delivering 9.5x higher energy efficiency.

}, keywords = {psclab}, doi = {10.1145/3154839}, url = {https://dl.acm.org/citation.cfm?id=3154839}, author = {YIxing Li and Zichuan Liu and Kai Xu and Hao Yu and Fengbo Ren} } @inproceedings {Orleans, Louisana, title = {SqueezedText: A Real-time Scene Text Recognition by Binary Convolutional Encoder-decoder Network}, year = {2018}, month = {04/2018}, pages = {7194-7201}, address = {New Orleans, Louisana}, abstract = {

A new approach for real-time scene text recognition is proposed in this paper. A novel binary convolutional encoderdecoder network (B-CEDNet) together with a bidirectional recurrent neural network (Bi-RNN). The B-CEDNet is engaged as a visual front-end to provide elaborated character detection, and a back-end Bi-RNN performs characterlevel sequential correction and classification based on learned contextual knowledge. The front-end B-CEDNet can process multiple regions containing characters using a one-off forward operation, and is trained under binary constraints with significant compression. Hence it leads to both remarkable inference run-time speedup as well as memory usage reduction. With the elaborated character detection, the back-end Bi-RNN merely processes a low dimension feature sequence with category and spatial information of extracted characters for sequence correction and classification. By training with over 1,000,000 synthetic scene text images, the B-CEDNet achieves a recall rate of 0.86, precision of 0.88 and F-score of 0.87 on ICDAR-03 and ICDAR-13. With the correction and classification by Bi-RNN, the proposed real-time scene text recognition achieves state-of-the-art accuracy while only consumes less than 1-ms inference run-time. The flow processing flow is realized on GPU with a small network size of 1.01 MB for B-CEDNet and 3.23 MB for Bi-RNN, which is much faster and smaller than the existing solutions.

}, keywords = {psclab}, author = {Zichuan Liu and YIxing Li and Fengbo Ren and Hao Yu and Wangling Goh} } @article {2016, title = {Data-Driven Sampling Matrix Boolean Optimization for Energy-Efficient Biomedical Signal Acquisition by Compressive Sensing}, journal = {IEEE Transactions on Biomedical Circuits and Systems}, volume = {11}, year = {2017}, month = {11/2016}, pages = {255-266}, abstract = {

Compressive sensing is widely used in biomedical applications, and the sampling matrix plays a critical role on both quality and power consumption of signal acquisition. It projects a high-dimensional vector of data into a low-dimensional subspace by matrix-vector multiplication. An optimal sampling matrix can ensure accurate data reconstruction and/or high compression ratio. Most existing optimization methods can only produce real-valued embedding matrices that result in large energy consumption during data acquisition. In this paper, we propose an efficient method that finds an optimal Boolean sampling matrix in order to reduce the energy consumption. Compared to random Boolean embedding, our data-driven Boolean sampling matrix can improve the image recovery quality by 9 dB. Moreover, in terms of sampling hardware complexity, it reduces the energy consumption by 4.6\× and the silicon area by 1.9\× over the data-driven real-valued embedding.

}, keywords = {psclab}, author = {Wang, Yuhao and Li, Xin and Xu, Kai and Ren, Fengbo and Yu, Hao} } @inproceedings {2016, title = {A Binary Convolutional Encoder-decoder Network for Real-time Natural Scene Text Processing}, year = {2016}, month = {12/2016}, abstract = {

In this paper, we develop a binary convolutional encoder-decoder network (B-CEDNet) for natural scene text processing (NSTP). It converts a text image to a class-distinguished salience map that reveals the categorical, spatial and morphological information of characters. The existing solutions are either memory consuming or run-time consuming that cannot be applied to real-time applications on resource-constrained devices such as advanced driver assistance systems. The developed network can process multiple regions containing characters by one-off forward operation, and is trained to have binary weights and binary feature maps, which lead to both remarkable inference run-time speedup and memory usage reduction. By training with over 200, 000 synthesis scene text images (size of 32 \× 128), it can achieve 90\% and 91\% pixel-wise accuracy on ICDAR-03 and ICDAR-13 datasets. It only consumes 4.59 ms inference run-time realized on GPU with a small network size of 2.14 MB, which is up to 8\× faster and 96\% smaller than it full-precision version.\ 

}, keywords = {psclab}, author = {Liu, Zichuan and Yixing Li and Ren, Fengbo and Yu, Hao} } @inproceedings {104, title = {A Compressive-sensing based Testing Vehicle for 3D TSV Pre-bond and Post-bond Testing Data}, year = {2016}, month = {04/2016}, pages = {19-25}, abstract = {

Online testing vehicle is required for 3D TSV pre-bond and post-bond testing due to high probability of TSV failures. It has become a challenge to deal with large sets of generated testing data with limited probing when transmitting the data out. In this paper, a lossless compressive-sensing based testing vehicle is developed for online testing of TSVs. By exploring sparsity of the testing data under constraint of failure bound of TSV, sparse-representation based encoding can be deployed by XOR and AND network on chip to deal with large volume of testing data. Experimental results (with benchmarks) have shown that 89.70\% pre-bond data compression rate can be achieved under 0.5\% probability of failures; and 88.18\% post-bond data compression rate can be achieved with 5\% probability of failures.

}, keywords = {psclab}, author = {Hantao Huang and Hao Yu and Cheng Zhuo and Fengbo Ren} } @article {32, title = {Body Voltage Sensing Based Short Pulse Reading Circuit}, number = {PCT/US2012/056136}, year = {2014}, month = {Mar 28, 2013}, chapter = {WO2013043738A1}, abstract = {

As memory geometries continue to scale down, current density of magnetic tunnel junctions (MTJs) make conventional low current reading scheme problematic with regard to performance and reliability. A body-voltage sense circuit (BVSC) short pulse reading (SPR) circuit is described using body connected load transistors and a novel sensing circuit with second stage amplifier which allows for very short read pulses providing much higher read margins, less sensing time, and shorter sensing current pulses. Simulation results (using 65-nm CMOS model SPICE simulations) show that our technique can achieve 550 mV of read margin at 1 ns performance under a 1 V supply voltage, which is greater than reference designs achieve at 5 ns performance.

}, keywords = {psclab}, issn = {US8917562B2}, url = {http://www.google.com/patents/WO2013043738A1}, author = {Kang-Lung Wang and Chih-Kong K. Yang and Dejan Markovic and Fengbo Ren} } @inproceedings {30, title = {Proper Running Posture Guide: A Wearable Biomechanics Capture System}, year = {2013}, month = {09/2013}, publisher = {ICST (Institute for Computer Sciences, Social-Informatics and Telecommunications Engineering)}, abstract = {

Running is a popular exercise for all age groups. It helps heart and lung functions, enhances muscle strength and control weight. Nevertheless, excessive fatigue and severe injury resulting from inappropriate running poses might reduce the benefits brought by this exercise and stop people from keeping running regularly. In this paper, we design a system that can monitor the running biomechanics, infer running poses, analyze running patterns, and provide both real-time and off-line feedbacks to reduce unnecessary fatigue and unwanted injuries. Common inappropriate running patterns, over-striding, over-pronating and out-sync, are identified and analyzed with the continuous wearable sensor data streams. Two types of correctional feedbacks are designed to provide users appropriate adjustment guidance: vibrating the areas of user body where improper poses are detected and visualizing running video with sensor waveforms to indicate which inappropriate motions trigger the vibration. With reasonable adjustment, running can be a safe and effective activity for a healthy lifestyle.

}, keywords = {psclab}, url = {http://dl.acm.org/citation.cfm?id=2555333}, author = {Zhang, Xiaoyi and Huang, Ming-Chun and Ren, Fengbo and Xu, Wenyao and Guan, Nan and Yi, Wang} } @article {20, title = {Reference Calibration of Body-voltage Sensing Circuit for High-speed STT-RAMs}, journal = {IEEE Transactions on Circuits and Systems I: Regular Papers}, volume = {60}, year = {2013}, month = {Apr.}, pages = {2932{\textendash}2939}, abstract = {

With the continuing scaling of MTJ, the high-speed reading of STT-RAM becomes increasingly difficult. Recently, a body-voltage sensing circuit (BVSC) has been proposed for boosting the sensing speed. This paper analyzes the effectiveness of using the reference calibration technique to compensate for the device mismatches and improve the read margin of BVSC. HSPICE simulation results show that a 2-bit reference calibration can improve the worst-case read margin in a 1-Mb memory by over 3 times. This leads to up to 30\% higher yield across all process corners. In order to maintain the yield improvement even in the worst-case corner, independent calibration circuitry has to be deployed for each memory array.

}, keywords = {psclab}, url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6492140}, author = {Ren, Fengbo and Park, Henry and Yang, C-KK and Markovi{\'c}, Dejan} } @inproceedings {28, title = {A Body-voltage-sensing-based Short Pulse Reading Circuit for Spin-torque Transfer RAMs (STT-RAMs)}, year = {2012}, month = {03/2012}, pages = {275-282}, publisher = {IEEE}, abstract = {

With scaling of CMOS and Magnetic Tunnel Junction (MTJ) devices, conventional low-current reading techniques for STT-RAMs face challenges in achieving reliability and performance improvements that are expected from scaled devices. The challenges arise from the increasing variability of the CMOS sensing current and the reduction in MTJ switching current. This paper proposes a short-pulse reading circuit, based on a body-voltage sensing scheme to mitigate the scaling issues. Compared to existing sensing techniques, our technique shows substantially higher read margin (RM) despite a much shorter sensing time. A narrow current pulse applied to an MTJ significantly reduces the probability of read disturbance. The RM analysis is validated by Monte-Carlo simulations in a 65-nm CMOS technology with both CMOS and MTJ variations considered. Simulation results show that our technique is able to provide over 300 mV RM at a GHz frequency across process-voltage-temperature (PVT) variations, while the reference designs require 4.3 ns and 2.3 ns sensing time for a 200 mV RM, respectively. The effective read energy per bit required by the proposed sensing circuit is around 195 ft in the nominal case.

}, keywords = {psclab}, url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6187506}, author = {Ren, Fengbo and Park, Henry and Dorrance, Richard and Toriyama, Yuta and Yang, C-KK and Markovi{\'c}, Dejan} } @article {18, title = {Scalability and Design-space Analysis of A 1T-1MTJ Memory Cell For STT-RAMs}, journal = {IEEE Transactions on Electron Devices}, volume = {59}, year = {2012}, month = {Jan.}, pages = {878{\textendash}887}, abstract = {

We present a design-space feasibility region, as a function of magnetic tunnel junction (MTJ) characteristics and target memory specifications, to explore the design margin of a one-transistor-one-magnetic-tunnel-junction (1T-1MTJ) memory cell for spin-transfer torque random access memories (STT-RAMs). Data from measured devices are used to model the statistical variation of an MTJ{\textquoteright}s critical switching current and resistance. The sensitivity of the design space to different design parameters is also analyzed for the scaling of both the MTJ and the underlying transistor technology. A design flow, using a sensitivity-based analysis and an MTJ switching model based on the Landau-Lifshitz-Gilbert equation, is proposed to optimize design margins for gigabit-scale memories. Design points for improved yield, density, and memory performance are extracted from MTJ-compatible complementary metal-oxide-semiconductor (CMOS) technologies for 90-, 65-, 45-, and 32-nm processes. Predictive technology models are used to explore the future scalability of STT-RAMs in upcoming 22- and 16-nm technology nodes. Our analysis shows that, to achieve Flash-like densities ( \<; 6F2) in advanced CMOS technologies, aggressive scaling of the critical switching current density will be required.

}, keywords = {psclab}, url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6140952}, author = {Dorrance, Richard and Ren, Fengbo and Toriyama, Yuta and Hafez, Amr Amin and Yang, C-KK and Markovi{\'c}, Dejan} } @inproceedings {25, title = {Analysis of STT-RAM Cell Design With Multiple MTJs Per Access}, year = {2011}, month = {01/2011}, pages = {53-58}, publisher = {IEEE Computer Society}, abstract = {

Density of STT-RAMs is limited by the area cost and width of the access device in a cell since it needs to support the programming currents. This paper explores a cell structure that shares each cell{\textquoteright}s access transistor with multiple MTJ memory elements. Feasibility and limitations of such a cell structure is explored for both reading and writing of the memory. The analytical and simulation results indicate that only small amount of sharing is possible and having MTJs that can handle a high read current without disturbing the cell is needed.

}, keywords = {psclab}, url = {http://dl.acm.org/citation.cfm?id=2052103}, author = {Park, Henry and Dorrance, Richard and Amin, Amr and Ren, Fengbo and Markovi{\'c}, Dejan and Ken Yang, CK} } @inproceedings {24, title = {Scalability And Design-space Analysis of A 1T-1MTJ Memory Cell}, year = {2011}, month = {01/2011}, pages = {32-36}, publisher = {IEEE}, abstract = {

This paper introduces a design-space feasibility region as a function of MTJ characteristics and memory target specifications. The sensitivity of the design space is analyzed for scaling of both MTJ and underlying transistor technology. Design points for improved yield, density, and memory performance can be extracted for 90nm down to 32nm processes based on measured MTJ devices. To achieve flash-like densities in upcoming 22nm and 16nm technology nodes, scaling of the critical switching current density is required.

}, keywords = {psclab}, url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5941480}, author = {Dorrance, Richard and Ren, Fengbo and Toriyama, Yuta and Amin, Amr and Yang, C-KK and Markovi{\'c}, Dejan} }