@inproceedings {497, title = {HALO 1.0: A Hardware-agnostic Accelerator Orchestration Framework for Enabling Hardware-agnostic Programming with True Performance Portability for Heterogeneous HPC}, year = {Under Review}, abstract = {

Hardware-agnostic programming with high performance portability will be the bedrock for realizing the ubiquitous adoption of emerging accelerator technologies in future heterogeneous high-performance computing (HPC) systems, which is the key to achieving the next level of HPC performance on an expanding accelerator landscape. In this paper, we present HALO 1.0, an open-ended extensible multi-agent software framework, that implements a set of proposed hardware-agnostic accelerator orchestration (HALO) principles and a novel compute-centric message passing interface (C2MPI) specification for enabling the portable and performance-optimized execution of hardware-agnostic application codes across heterogeneous accelerator resources. The experiment results of evaluating eight widely used HPC subroutines based on Intel Xeon E5-2620 v4 CPUs, Intel Arria 10 GX FPGAs, and NVIDIA GeForce RTX 2080 Ti GPUs show that HALO 1.0 allows the same hardware-agnostic application codes of the HPC kernels, without any change, to run across all the computing devices with a consistently maximum performance portability score of 1.0, which is 2x-861,883x higher than the OpenCL-based solution that suffers from an unstably low performance portability score.

}, keywords = {psclab}, url = {https://arxiv.org/pdf/2011.10896.pdf}, author = {Michael Riera and Bank-Tavakoli, Erfan and Masudul Hassan Quraishi and Fengbo Ren} } @inproceedings {Rhodes Island, Greece, title = {Automatic Error Detection in Integrated Circuits Image Segmentation: A Data-driven Approach}, year = {2023}, month = {06/2023}, address = {Rhodes Island, Greece}, keywords = {psclab}, author = {Zhikang Zhang and Bruno Machado Trindade and Michael Green and Zifan Yu and Christopher Pawlowicz and Fengbo Ren} } @inproceedings {Rhodes Island, Greece, title = {Enhanced Low-resolution LiDAR-Camera Calibration Via Depth Interpolation and Supervised Contrastive Learning}, year = {2023}, month = {06/2023}, address = {Rhodes Island, Greece}, keywords = {psclab}, author = {Zhikang Zhang and Zifan Yu and Suya You and Raghuveer Rao and Sanjeev Agarwal and Fengbo Ren} } @inproceedings {Bordeaux, France, title = {A Data-Driven Approach for Automated Integrated Circuit Segmentation of Scan Electron Microscopy Images}, year = {2022}, month = {10/2022}, address = {Bordeaux, France}, abstract = {

This paper proposes an automated data-driven integrated
circuit segmentation approach of scan electron microscopy
(SEM) images inspired by state-of-the-art CNN-based image
perception methods. Based on the requirements derived from
real industry applications, we take wire segmentation and via
detection algorithms to generate integrated circuit segmentation
maps from SEMs in our approach. On SEM images
collected in the industrial applications, our method achieves
an average of 50.71 on Electrically Significant Difference
(ESD) in the wire segmentation task and 99.05\% F1 score
in the via detection task, which achieves about 85\% and 8\%
improvements over the reference method, respectively.

}, keywords = {psclab}, author = {Zifan Yu and Bruno Machado Trindade and Michael Green and Zhikang Zhang and Pullela Sneha and Bank-Tavakoli, Erfan and Christopher Pawlowicz and Ren, Fengbo} } @inproceedings {Singapore, title = {An Experimental Study on Transferring Data-Driven Image Compressive Sensing to Bioelectric Signals}, year = {2022}, month = {05/2022}, pages = {1191-1195}, address = {Singapore}, abstract = {

The emerging area of bioelectric signal compressive sensing(CS) has shown great potential in health care applications. However, improving the reconstruction accuracy of compressively sensed bioelectric signals remains a challenging problem. In recent years, data-driven image CS methods have achieved significant improvements in reconstruction ac- curacy over conventional model-based image CS methods. In this paper, we conduct an experimental study on transferring existing data-driven image CS methods to bioelectric signals. Through our investigation of five critical factors affecting the reconstruction performance of bioelectric signals, we conclude that existing data-driven image CS methods can be transferred to ECG signals with high reconstruction accuracy. Our experimental results show that transferred data-driven image CS methods can achieve up to 8.08-2.73 SNR improvement over the reference method on ECG signal reconstruction across compression ratios of 2-8x.

}, keywords = {psclab}, doi = {10.1109/ICASSP43922.2022.9747439}, author = {Zhikang Zhang and Jonathan Zhao and Fengbo Ren} } @inproceedings {London, UK, title = {STPLS3D: A Large-Scale Synthetic and Real Aerial Photogrammetry 3D Point Cloud Dataset}, year = {2022}, month = {11/2022}, address = {London, UK}, abstract = {

Although various 3D datasets with different functions and scales have been proposed recently, it remains challenging for individuals to complete the whole pipeline of large- scale data collection, sanitization, and annotation. Moreover, the created datasets usually face the challenge of extremely imbalanced class distribution or partial low-quality data samples. Motivated by this, we explore the procedurally synthetic 3D data generation paradigm to equip individuals with the full capability of creating large-scale annotated photogrammetry point clouds. Specifically, we introduce a synthetic aerial photogrammetry point clouds generation pipeline that takes full advantage of open geospatial data sources and off-the-shelf commercial packages. Unlike generating synthetic data in virtual games, where the simulated data usually have limited gaming environments created by artists, the proposed pipeline simulates the reconstruction process of the real environment by following the same UAV flight pattern on different synthetic terrain shapes and building densities, which ensure similar quality, noise pattern, and diversity with real data. In addition, the precise semantic and instance annotations can be generated fully automatically, avoiding the expensive and time-consuming manual annotation. Based on\ the proposed pipeline, we present a richly-annotated synthetic 3D aerial photogrammetry point cloud dataset, termed STPLS3D, with more than 16 km2 of landscapes and up to 18 fine-grained semantic categories. For verification purposes, we also provide datasets collected from four areas in the real environment. Extensive experiments conducted on our datasets demonstrate the effectiveness and quality of the proposed synthetic dataset.

}, keywords = {psclab}, url = {https://www.stpls3d.com/}, author = {Meida Chen and Qingyong Hu and Zifan Yu and Hugues Thomas and Andrew Feng and Yu Hou and Kyle McCullough and Fengbo Ren and Lucio Soibelman} } @inproceedings {Virtual Event, title = {FSCHOL: An OpenCL-based HPC Framework for Accelerating Sparse Cholesky Factorization on FPGAs}, year = {2021}, month = {10/2021}, pages = {209-220}, address = {Virtual Event}, abstract = {

The proposed FSCHOL framework consists of an FPGA kernel implementing a throughput-optimized hardware architecture for accelerating the supernodal multifrontal algorithm for sparse Cholesky factorization and a host program implementing a novel scheduling algorithm for finding the optimal execution order of supernodes computations for an elimination tree on the FPGA to eliminate the need for off-chip memory access for storing intermediate results. Moreover, the proposed scheduling algorithm minimizes on-chip memory requirements for buffering intermediate results by resolving the dependency of parent nodes in an elimination tree through temporal parallelism. Experiment results for factorizing a set of sparse matrices in various sizes from SuiteSparse Matrix Collection show that the proposed FSCHOL implemented on an Intel Stratix 10 GX FPGA development board achieves on average 5.5\× and 9.7\× higher performance and 10.3\× and 24.7\× lower energy consumption than implementations of CHOLMOD on an Intel Xeon E5-2637 CPU and an NVIDIA V100 GPU, respectively.

}, keywords = {psclab}, doi = {10.1109/SBAC-PAD53543.2021.00032}, author = {Erfan Bank-Tavakoli and Michael Riera and Masudul Hassan Quraishi and Fengbo Ren} } @article {561, title = {OpenICS: Open Image Compressive Sensing Toolbox and Benchmark}, journal = {Software Impacts}, volume = {9}, year = {2021}, month = {05/2021}, abstract = {

The real-world application of image compressive sensing is largely limited by the lack of standardization in implementation and evaluation. To address this limitation, we present OpenICS, an image compressive sensing toolbox that implements multiple popular image compressive sensing algorithms into a unified framework with a standardized user interface. Furthermore, a corresponding benchmark is also proposed to provide a fair and complete evaluation of the implemented algorithms. We hope this work can serve the growing research community of compressive sensing and the industry to facilitate the development and application of image compressive sensing.

}, keywords = {psclab}, doi = {https://doi.org/10.1016/j.simpa.2021.100081}, url = {https://arxiv.org/pdf/2103.00652.pdf}, author = {Jonathan Zhao and Matthew Westerham and Mark Lakatos-Toth and Zhikang Zhang and Avi Moskoff and Fengbo Ren} } @article {498, title = {A Survey of System Architectures and Techniques for FPGA Virtualization}, journal = { IEEE Transactions on Parallel and Distributed Systems}, volume = {32}, year = {2021}, month = {09/2021}, pages = {2216-2230}, abstract = {

FPGA accelerators are gaining increasing attention in both cloud and edge computing because of their hardware flexibility, high computational throughput, and low power consumption. However, the design flow of FPGAs often requires specific knowledge of the underlying hardware, which hinders the wide adoption of FPGAs by application developers. Therefore, the virtualization of FPGAs becomes extremely important to create a useful abstraction of the hardware suitable for application developers. Such abstraction also enables the sharing of FPGA resources among multiple users and accelerator applications, which is important because, traditionally, FPGAs have been mostly used in single-user, single-embedded-application scenarios. There are many works in the field of FPGA virtualization covering different aspects and targeting different application areas. In this survey, we review the system architectures used in the literature for FPGA virtualization. In addition, we identify the primary objectives of FPGA virtualization, based on which we summarize the techniques for realizing FPGA virtualization. This survey helps researchers to efficiently learn about FPGA virtualization research by providing a comprehensive review of the existing literature.

}, keywords = {psclab}, issn = {1045-9219}, doi = {10.1109/TPDS.2021.3063670}, author = {Masudul Hassan Quraishi and Erfan Bank-Tavakoli and Fengbo Ren} } @inproceedings {Santa Clara, CA, title = {BNN Pruning: Pruning Binary Neural Network Guided by Weight Flipping Frequency}, year = {2020}, month = {03/2020}, address = {Santa Clara, CA}, abstract = {
A binary neural network (BNN) is a compact form of neural network. Both the weights and activations in BNNs can be binary values, which leads to a significant reduction in both parameter size and computational complexity compared to their full-precision counterparts. Such reductions can directly translate into reduced memory footprint and computation cost in hardware, making BNNs highly suitable for a wide range of hardware accelerators. However, it is unclear whether and how a BNN can be further pruned for ultimate compactness. As both 0s and 1s are non-trivial in BNNs, it is not proper to adopt any existing pruning method of full- precision networks that interprets 0s as trivial. In this paper, we present a pruning method tailored to BNNs and illustrate that BNNs can be further pruned by using weight flipping frequency as an indicator of sensitivity to accuracy. The experiments performed on the binary versions of a 9- layer Network-in-Network (NIN) and the AlexNet with the CIFAR-10 dataset show that the proposed BNN-pruning method can achieve 20-40\% reduction in binary operations with 0.5-1.0\% accuracy drop, which leads to a 15-40\% run- time speedup on a TitanX GPU.
}, keywords = {psclab}, author = {YIxing Li and Fengbo Ren} } @article {359, title = {Build a Compact Binary Neural Network through Bit-level Sensitivity and Data Pruning}, journal = { Neurocomputing}, volume = {398}, year = {2020}, month = {07/2020}, pages = {45-54}, abstract = {

Due to the high computational complexity and memory storage requirement, it is hard to directly de- ploy a full-precision convolutional neural network (CNN) on embedded devices. The hardware-friendly designs are needed for resource-limited and energy-constrained embedded devices. Emerging solutions are adopted for the neural network compression, e.g., binary/ternary weight network, pruned network and quantized network. Among them, binary neural network (BNN) is believed to be the most hardware- friendly framework due to its small network size and low computational complexity. No existing work has further shrunk the size of BNN. In this work, we explore the redundancy in BNN and build a com- pact BNN (CBNN) based on the bit-level sensitivity analysis and bit-level data pruning. The input data is converted to a high dimensional bit-sliced format. In the post-training stage, we analyze the impact of different bit slices to the accuracy. By pruning the redundant input bit slices and shrinking the network size, we are able to build a more compact BNN. Our result shows that we can further scale down the net- work size of the BNN up to 3.9x with no more than 1\% accuracy drop. The actual runtime can be reduced up to 2x and 9.9x compared with the baseline BNN and its full-precision counterpart, respectively.

}, keywords = {psclab}, author = {YIxing Li and Shuai Zhang and Xichuan Zhou and Fengbo Ren} } @inproceedings {Barcelona, Spain, title = {CRA: A Generic Compression Ratio Adaptor for End-to-end Data-driven Image Compressive Sensing Reconstruction Frameworks}, year = {2020}, month = {05/2020}, pages = {1740-1749}, address = {Barcelona, Spain}, abstract = {

End-to-end data-driven image compressive sensing reconstruction (EDCSR) frameworks achieve state-of-the-art reconstruction performance in terms of reconstruction speed and accuracy. However, due to their end-to-end nature, existing EDCSR frameworks can not adapt to a variable compression ratio (CR). For applications that desire a variable CR, existing EDCSR frameworks must be trained from scratch at each CR, which is computationally costly and time-consuming. This paper presents a generic compression ratio adapter (CRA) framework that addresses the variable compression ratio (CR) problem for existing EDCSR frameworks with no modification to given reconstruction models nor enormous rounds of training needed. CRA exploits an initial reconstruction network to generate an initial estimate of reconstruction results based on a small portion of the acquired measurements. Subsequently, CRA approximates full measurements for the main reconstruction network by complementing the sensed measurements with resensed initial estimate. Our experiments based on two public image datasets (CIFAR10 and Set5) show that CRA provides an average of 13.02 dB and 5.38 dB PSNR improvement across the CRs from 5 to 30 over a naive zero-padding approach and the AdaptiveNN approach(a prior work), respectively. CRA addresses the fixed-CR limitation of existing EDCSR frameworks and makes them suitable for resource-constrained compressive sensing applications.

}, keywords = {psclab}, author = {Zhikang Zhang and Kai Xu and Fengbo Ren} } @article {562, title = {LAPRAN: A SCALABLE LAPLACIAN PYRAMID RECONSTRUCTIVE ADVERSARIAL NETWORK FOR FLEXIBLE COMPRESSIVE SENSING RECONSTRUCTION}, number = {16/745,817}, year = {2020}, month = {07/2020}, keywords = {psclab}, author = {Fengbo Ren and Kai Xu and Zhikang Zhang} } @inproceedings {Seattle, WA, title = {Learning in the Frequency Domain}, year = {2020}, month = {06/2020}, pages = {1740-1749}, address = {Seattle, WA}, abstract = {

Deep neural networks have achieved remarkable success in computer vision tasks. Existing neural networks mainly operate in the spatial domain with fixed input sizes. For practical applications, images are usually large and have to be downsampled to the predetermined input size of neural networks. Even though the downsampling operations reduce computation and the required communication bandwidth, it removes both redundant and salient information obliviously, which results in accuracy degradation. Inspired by digital signal processing theories, we analyze the spectral bias from the frequency perspective and propose a learning-based frequency selection method to identify the trivial frequency components which can be removed with- out accuracy loss. The proposed method of learning in the frequency domain leverages identical structures of the well- known neural networks, such as ResNet-50, MobileNetV2, and Mask R-CNN, while accepting the frequency-domain information as the input. Experiment results show that learning in the frequency domain with static channel selection can achieve higher accuracy than the conventional spatial downsampling approach and meanwhile further reduce the input data size. Specifically for ImageNet classification with the same input size, the proposed method achieves 1.41\% and 0.66\% top-1 accuracy improvements on ResNet-50 and MobileNetV2, respectively. Even with half input size, the proposed method still improves the top-1 accuracy on ResNet-50 by 1\%. In addition, we observe a 0.8\% average precision improvement on Mask R-CNN for instance segmentation on the COCO dataset.

}, keywords = {psclab}, author = {Kai Xu and Minghai Qin and Fei Sun and Yuhao Wang and Yen-Kuang Chen and Fengbo Ren} } @inproceedings {New Orleans, Louisiana, title = {Light-Weight RetinaNet for Object Detection on Edge Devices}, year = {2020}, month = {04/2020}, address = {New Orleans, Louisiana}, abstract = {

This paper aims at reducing computation for Reti\­nanet, an mAP-30-tier network, to facilitate its practical deploy\­ment on edge devices for providing IoT-based object detection services. We first validate RetinaNet has the best FLOP-mAP trade-off among all mAP-30-tier network. Then, we propose a light-weight RetinaNet structure with effective computation\­-accuracy trade-off by only reducing FLOPs in computationally intensive layers. Compared with the most common way of trading off computation with accuracy-input image scaling, the proposed solution shows a consistently better FLOPs-mAP trade-off curve. Light-weight RetinaNet achieves a 0.3\% mAP improvement at 1.Sx FLOPs reduction point over the original RetinaNet, and gains 1.Sx more energy-efficiency on an Intel Arria 10 FPGA accelerator in the context of edge computing. The proposed method potentially can help a wide range of the object detection applications to move closer to a preferred corner for a better runtime and accuracy, while enjoys more energy-efficient inference at the edge.\ 

}, keywords = {psclab}, author = {YIxing Li and Akshay Dua and Fengbo Ren} } @inproceedings {Virtual Event, title = {MoNet3D: Towards Accurate Monocular 3D Object Localization in Real Time}, year = {2020}, month = {07/2020}, address = {Virtual Event}, abstract = {

Monocular multi-object detection and localization in 3D space has been proven to be a challenging task. The MoNet3D algorithm is a novel and effective framework that can predict the 3D position of each object in a monocular image and draw a 3D bounding box for each object. The MoNet3D method incorporates prior knowledge of the spatial geometric correlation of neighboring objects into the deep neural network training process to improve the accuracy of 3D object localization. Experiments on the KITTI dataset show that the accuracy for predicting the depth and horizontal coordinates of objects in 3D space can reach 96.25\% and 94.74\%, respectively. Moreover, the method can realize the real-time image processing at 27.85 FPS, showing promising potential for embedded advanced driving assistance system applications. Our code is publicly available at

}, keywords = {psclab}, author = {Xichuan Zhou and Yicong Peng and Chunqiao Long and Fengbo Ren and Cong Shi} } @article {414, title = {A Review of Algorithm \& Hardware Design for AI-Based Biomedical Applications}, journal = {IEEE Transactions on Biomedical Circuits and Systems }, volume = {14}, year = {2020}, month = {04/2020}, pages = {145-163}, abstract = {

This paper reviews the state of the arts and trends of the AI-based biomedical processing algorithms and hardwares. The algorithms and hardwares for different biomedical applications such as ECG, EEG and hearing aid have been reviewed and discussed. For algorithm design, various widely used biomedical signal classification algorithms have been discussed including support vector machine (SVM), back propagation neural network (BPNN), convolutional neural networks (CNN), probabilistic neural networks (PNN), recurrent neural networks (RNN), Short-term Memory Network (LSTM), fuzzy neural network and etc. The pros and cons of the classification algorithms have been analyzed and compared in the context of application scenarios. The research trends of AI-based biomedical processing algorithms and applications are also discussed. For hardware design, various AI-based biomedical processors have been reviewed and discussed, including ECG classification processor, EEG classification processor, EMG classification processor and hearing aid processor. Various techniques on architecture and circuit level have been analyzed and compared. The research trends of the AI-based biomedical processor have also been discussed.

}, keywords = {psclab}, issn = {1940-9990}, doi = {10.1109/TBCAS.2020.2974154}, author = {Ying Wei and Jun Zhou and Yin Wang and Yinggang Liu and Qingsong Liu and Jiansheng Luo and Chao Wang and Fengbo Ren and Li Huang} } @article {499, title = {Systolic-CNN: An OpenCL-defined Scalable Run-time-flexible FPGA Accelerator Architecture for Accelerating Convolutional Neural Network Inference in Cloud/Edge Computing}, year = {2020}, month = {12/2020}, abstract = {

This paper presents Systolic-CNN, an OpenCL-defined scalable, runtime-flexible FPGA accelerator architecture, optimized for accelerating the inference of various convolutional neural networks (CNNs) in multi-tenancy cloud/edge computing. The existing OpenCL-defined FPGA accelerators for CNN inference are insufficient due to limited flexibility for supporting multiple CNN models at run time and poor scalability resulting in underutilized FPGA resources and limited computational parallelism. Systolic-CNN adopts a highly pipelined and paralleled 1-D systolic array architecture, which efficiently explores both spatial and temporal parallelism for accelerating CNN inference on FPGAs. Systolic-CNN is highly scalable and parameterized, which can be easily adapted by users to achieve up to 100\% utilization of the coarse-grained computation resources (i.e., DSP blocks) for a given FPGA. Systolic-CNN is also run-time-flexible in the context of multi-tenancy cloud/edge computing, which can be time-shared to accelerate a variety of CNN models at run time without the need of recompiling the FPGA kernel hardware nor reprogramming the FPGA. The experiment results based on an Intel Arria/Stratix 10 GX FPGA Development board show that the optimized single-precision implementation of Systolic-CNN can achieve an average inference latency of 7ms/2ms, 84ms/33ms, 202ms/73ms, 1615ms/873ms, and 900ms/498ms per image for accelerating AlexNet, ResNet-50, ResNet-152, RetinaNet, and Light-weight RetinaNet, respectively. Codes are available at https://github.com/PSCLab-ASU/Systolic-CNN.

}, keywords = {psclab}, url = {https://arxiv.org/pdf/2012.03177.pdf}, author = {Akshay Dua and YIxing Li and Fengbo Ren} } @article {379, title = {A 34-FPS 698-GOP/s/W Binarized Deep Neural Network-based Natural Scene Text Interpretation Accelerator for Mobile Edge Computing}, journal = {IEEE Transactions on Industrial Electronics (TIE)}, volume = {66}, year = {2019}, month = {10/2018}, pages = {7407-7416}, abstract = {

The scene text interpretation is a critical part of natural scene interpretation. Currently, most of the existing work is based on high-end GPU implementation, which is commonly used on the server side. However, in IoT application scenarios, the communication overhead from the edge device to the server is quite large, which sometimes even dominates the total processing time. Hence, the edgecomputing oriented design is needed to solve this problem. In this paper, we present an architectural design and implementation of a natural scene text interpretation (NSTI) accelerator, which can classify and localize the text region on pixel-level efficiently in real-time on mobile devices. To target the real-time and low-latency processing, the Binary Convolutional Encoder-decoder Network (B-CEDNet) is adopted as the core architecture to enable massive parallelism due to its binary feature. Massively parallelized computations and a highly pipelined data flow control enhance its latency and throughput performance. In addition, all the binarized intermediate results and parameters are stored on chip to eliminate the power consumption and latency overhead of the off-chip communication. The NSTI accelerator is implemented in a 40nm CMOS technology, which can process scene text images (size of 128x32) at 34 fps and latency of 40 ms for pixelwise interpretation with the pixelwise classification accuracy over 90\% on ICDAR- 03 and ICDAR-13 dataset. The real energy-efficiency is 698 GOP/s/W and the peak energy-efficiency can get up to 7825 GOP/s/W. The proposed accelerator is 7 more energy efficient than its optimized GPU-based implementation counterpart, while maintaining a real-time throughput with latency of 40 ms.

}, keywords = {psclab}, doi = {10.1109/TIE.2018.2875643}, url = {https://ieeexplore.ieee.org/document/8513982}, author = {YIxing Li and Zichuan Liu and Wenye Liu and Yu Jiang and Yongliang Wang and Wang Ling Goh and Hao Yu and Fengbo Ren} } @article {366, title = {A Deep Learning Approach for Targeted Contrast-Enhanced Ultrasound Based Prostate Cancer Detection}, journal = {IEEE/ACM Transactions on Computational Biology and Bioinformatics}, volume = {16}, year = {2019}, month = {05/2018}, pages = {1794-1801}, abstract = {

The important role of angiogenesis in cancer development has driven many researchers to investigate the prospects of noninvasive cancer diagnosis based on the technology of contrast-enhanced ultrasound (CEUS) imaging. This paper presents a deep learning framework to detect prostate cancer in the sequential CEUS images. The proposed method uniformly extracts features from both the spatial and the temporal dimensions by performing three-dimensional convolution operations, which captures the dynamic information of the perfusion process encoded in multiple adjacent frames for prostate cancer detection. The deep learning models were trained and validated against expert delineations over the CEUS images recorded using two types of contrast agents, i.e. the anti-PSMA based agent targeted to prostate cancer cells and the non-targeted blank agent. Experiments showed that the deep learning method achieved over 91\% specificity and 90\% average accuracy over the targeted CEUS images for prostate cancer detection, which was superior (p \< 0.05) than previously reported approaches and implementations.

}, keywords = {psclab}, doi = {10.1109/TCBB.2018.2835444}, url = {https://ieeexplore.ieee.org/document/8357938}, author = {Yujie Feng and Fan Yang and Xichuan Zhou and Yanli Guo and Fang Tang and Fengbo Ren and Jishun Guo and Shuiwang Ji} } @article {390, title = {Enabling Deep Learning for Edge Computing}, year = {2019}, keywords = {psclab}, author = {Baoxin Li and Fengbo Ren} } @article {421, title = {Real time end-to-end learning system for a high frame rate video compressive sensing network}, number = {US16/165,568}, year = {2019}, abstract = {

A real time end-to-end learning system for a high frame rate video compressive sensing network is described. The slow reconstruction speed of conventional compressive sensing approaches is overcome by directly modeling an inverse mapping from compressed domain to original domain in a single forward propagation. Through processing massive unlabeled video data such a mapping is learned by a neural network using data-driven methods. Systems and methods according to this disclosure incorporate a multi-rate convolutional neural network (CNN) and a synthesizing recurrent neural network (RNN) to achieve real time compression and reconstruction of video data.

}, keywords = {psclab}, issn = {US20190124346A1}, url = {https://patents.google.com/patent/US20190124346A1/en?inventor=Fengbo+Ren\&oq=inventor:(Fengbo+Ren)}, author = {Fengbo Ren and Kai Xu} } @inproceedings {360, title = {Are FPGAs Suitable for Edge Computing?}, year = {2018}, month = {07/2018}, address = {BOSTON, MA}, abstract = {

The rapid growth of Internet-of-things (IoT) and artificial intelligence applications have called forth a new computing paradigm\–edge computing. In this paper, we study the suitability of deploying FPGAs for edge computing from the perspectives of throughput sensitivity to workload size, architectural adaptiveness to algorithm characteristics, and energy efficiency. This goal is accomplished by conducting comparison experiments on an Intel Arria 10 GX1150 FPGA and an Nvidia Tesla K40m GPU. The experiment results imply that the key advantages of adopting FPGAs for edge computing over GPUs are three-fold: 1) FPGAs can provide a consistent throughput invariant to the size of application workload, which is critical to aggregating individual service requests from various IoT sensors; (2) FPGAs offer both spatial and temporal parallelism at a fine granularity and a massive scale, which guarantees a consistently high performance for accelerating both high-concurrency and high-dependency algorithms; and (3) FPGAs feature 3\– 4 times lower power consumption and up to 30.7 times better energy efficiency, offering better thermal stability and lower energy cost per functionality.

}, keywords = {psclab}, author = {Saman Biookaghazadeh and Ming Zhao and Fengbo Ren} } @inproceedings {270, title = {CSVideoNet: A Real-time End-to-end Learning Framework for High-frame-rate Video Compressive Sensing}, year = {2018}, month = {03/2018}, abstract = {

This paper addresses the real-time encoding-decoding problem for high-frame-rate video compressive sensing (CS). Unlike prior works that perform reconstruction using iterative optimization-based approaches, we propose a non-iterative model, named \“CSVideoNet\”. CSVideoNet directly learns the inverse mapping of CS and reconstructs the original input in a single forward propagation. To overcome the limitations of existing CS cameras, we propose a multi-rate CNN and a synthesizing RNN to improve the trade-o‚ between compression ratio (CR) and spatial-temporal resolution of the reconstructed videos. The experiment results demonstrate that CSVideoNet\ significantly\ outperforms the state-of-the-art approaches. With no pre/post-processing, we achieve 25dB PSNR recovery quality at 100x CR, with a frame rate of 125 fps on a Titan X GPU. Due to the feedforward and high-data-concurrency natures of CSVideoNet, it can take advantage of GPU acceleration to achieve three orders of magnitude speed-up over conventional iterative-based approaches. We share the source code at https://github.com/PSCLab-ASU/CSVideoNet.

}, keywords = {psclab}, doi = {10.1109/WACV.2018.00187}, author = {Kai Xu and Fengbo Ren} } @article {369, title = {A GPU-Outperforming FPGA Accelerator Architecture for Binary Convolutional Neural Networks}, journal = {ACM Journal on Emerging Technologies in Computing (JETC) - Special Issue on Frontiers of Hardware and Algorithms for On-chip Learning​}, volume = {14}, year = {2018}, month = {07/2018}, pages = {18.16}, chapter = {18.1}, abstract = {

FPGA-based hardware accelerators for convolutional neural networks (CNNs) have obtained great attentions due to their higher energy efficiency than GPUs. However, it is challenging for FPGA-based solutions to achieve a higher throughput than GPU counterparts. In this paper, we demonstrate that FPGA acceleration can be a superior solution in terms of both throughput and energy efficiency when a CNN is trained with binary constraints on weights and activations. Specifically, we propose an optimized FPGA accelerator architecture tailored for bitwise convolution and normalization that features massive spatial parallelism with deep pipelines stages. A key advantage of the FPGA accelerator is that its performance is insensitive to data batch size, while the performance of GPU acceleration varies largely depending on the batch size of the data. Experiment results show that the proposed accelerator architecture for binary CNNs running on a Virtex-7 FPGA is 8.3x faster and 75x more energy-efficient than a Titan X GPU for processing online individual requests in small batch sizes. For processing static data in large batch sizes, the proposed solution is on a par with a Titan X GPU in terms of throughput while delivering 9.5x higher energy efficiency.

}, keywords = {psclab}, doi = {10.1145/3154839}, url = {https://dl.acm.org/citation.cfm?id=3154839}, author = {YIxing Li and Zichuan Liu and Kai Xu and Hao Yu and Fengbo Ren} } @inproceedings {Munich, Germany, title = {LAPRAN: A Scalable Laplacian Pyramid Reconstructive Adversarial Network for Flexible Compressive Sensing Reconstruction}, year = {2018}, month = {09/2018}, pages = {491-507}, address = {Munich, Germany}, abstract = {

This paper addresses the single-image compressive sensing (CS) and reconstruction problem. We propose a scalable Laplacian pyramid reconstructive adversarial network (LAPRAN) that enables high- fidelity, flexible and fast CS images reconstruction. LAPRAN progressively reconstructs an image following the concept of the Laplacian pyramid through multiple stages of reconstructive adversarial networks (RANs). At each pyramid level, CS measurements are fused with a contextual latent vector to generate a high-frequency image residual. Consequently, LAPRAN can produce hierarchies of reconstructed images and each with an incremental resolution and improved quality. The scalable pyramid structure of LAPRAN enables high-fidelity CS reconstruction with a flexible resolution that is adaptive to a wide range of compression ratios (CRs), which is infeasible with existing methods. Experimental results on multiple public datasets show that LAPRAN offers an average 7.47dB and 5.98dB PSNR, and an average 57.93\% and 33.20 \% SSIM improvement compared to model-based and data-driven baselines, respectively.

}, keywords = {psclab}, author = {Kai Xu and Zhikang Zhang and Fengbo Ren} } @inproceedings {Orleans, Louisana, title = {SqueezedText: A Real-time Scene Text Recognition by Binary Convolutional Encoder-decoder Network}, year = {2018}, month = {04/2018}, pages = {7194-7201}, address = {New Orleans, Louisana}, abstract = {

A new approach for real-time scene text recognition is proposed in this paper. A novel binary convolutional encoderdecoder network (B-CEDNet) together with a bidirectional recurrent neural network (Bi-RNN). The B-CEDNet is engaged as a visual front-end to provide elaborated character detection, and a back-end Bi-RNN performs characterlevel sequential correction and classification based on learned contextual knowledge. The front-end B-CEDNet can process multiple regions containing characters using a one-off forward operation, and is trained under binary constraints with significant compression. Hence it leads to both remarkable inference run-time speedup as well as memory usage reduction. With the elaborated character detection, the back-end Bi-RNN merely processes a low dimension feature sequence with category and spatial information of extracted characters for sequence correction and classification. By training with over 1,000,000 synthetic scene text images, the B-CEDNet achieves a recall rate of 0.86, precision of 0.88 and F-score of 0.87 on ICDAR-03 and ICDAR-13. With the correction and classification by Bi-RNN, the proposed real-time scene text recognition achieves state-of-the-art accuracy while only consumes less than 1-ms inference run-time. The flow processing flow is realized on GPU with a small network size of 1.01 MB for B-CEDNet and 3.23 MB for Bi-RNN, which is much faster and smaller than the existing solutions.

}, keywords = {psclab}, author = {Zichuan Liu and YIxing Li and Fengbo Ren and Hao Yu and Wangling Goh} } @inproceedings {2016, title = {A Data-Driven Compressive Sensing Framework Tailored For Energy-Efficient Wearable Sensing}, year = {2017}, month = {03/2017}, pages = {861-865}, address = {New Orleans, LA}, abstract = {

Compressive sensing (CS) is a promising technology for realizing energy-efficient wireless sensors for long-term health monitoring. However, conventional model-driven CS frameworks suffer from limited compression ratio and reconstruction quality when dealing with physiological signals due to inaccurate models and the overlook of individual variability. In this paper, we propose a data-driven CS framework that can learn signal characteristics and personalized features from any individual recording of physiologic signals to enhance CS performance with a minimized number of measurements. Such improvements are accomplished by a co-training approach that optimizes the sensing matrix and the dictionary towards improved restricted isometry property and signal sparsity, respectively. Experimental results upon ECG signals show that the proposed method, at a compression ratio of 10x, successfully reduces the isometry constant of the trained sensing matrices by 86\% against random matrices and improves the overall reconstructed signal-to-noise ratio by 15dB over conventional model-driven approaches.\ 

}, keywords = {psclab}, author = {Xu, Kai and Yixing Li and Ren, Fengbo} } @article {2016, title = {Data-Driven Sampling Matrix Boolean Optimization for Energy-Efficient Biomedical Signal Acquisition by Compressive Sensing}, journal = {IEEE Transactions on Biomedical Circuits and Systems}, volume = {11}, year = {2017}, month = {11/2016}, pages = {255-266}, abstract = {

Compressive sensing is widely used in biomedical applications, and the sampling matrix plays a critical role on both quality and power consumption of signal acquisition. It projects a high-dimensional vector of data into a low-dimensional subspace by matrix-vector multiplication. An optimal sampling matrix can ensure accurate data reconstruction and/or high compression ratio. Most existing optimization methods can only produce real-valued embedding matrices that result in large energy consumption during data acquisition. In this paper, we propose an efficient method that finds an optimal Boolean sampling matrix in order to reduce the energy consumption. Compared to random Boolean embedding, our data-driven Boolean sampling matrix can improve the image recovery quality by 9 dB. Moreover, in terms of sampling hardware complexity, it reduces the energy consumption by 4.6\× and the silicon area by 1.9\× over the data-driven real-valued embedding.

}, keywords = {psclab}, author = {Wang, Yuhao and Li, Xin and Xu, Kai and Ren, Fengbo and Yu, Hao} } @inproceedings {Los Angeles, CA, title = {Recognizing terrain features on terrestrial surface using a deep learning model - An example with crater detection}, year = {2017}, month = {11/2017}, pages = {33-36}, publisher = {ACM}, address = {Los Angeles, CA}, abstract = {

This paper exploits the use of a popular deep learning model - the faster-RCNN - to support automatic terrain feature detection and classification using a mixed set of optimal remote sensing and natural images. Crater detection is used as the case study in this research since this geomorphological feature provides important information about surface aging. Craters, such as impact craters, also effect global changes in many aspects, such as geography, topography, mineral and hydrocarbon production, etc. The collected data were labeled and the network was trained through a GPU server. Experimental results show that the faster-RCNN model coupled with a widely used convolutional network ZF-net performs well in detecting craters on the terrestrial surface.

}, keywords = {psclab}, isbn = {978-1-4503-5498-1/17/11}, author = {Wenwen Li and Bin Zhou and Chia-Yu Hsu and YIxing Li and Fengbo Ren} } @article {9999, title = {An 8-Bit Compressive Sensing ADC With 4GS/s Equivalent Speed Utilizing Self-Timed Pipeline SAR-Binary-Search}, journal = {IEEE Transactions on Circuits and Systems II: Express Briefs}, volume = {63}, year = {2016}, month = {10/2016}, pages = {934-938}, abstract = {

This brief presents a 65nm CMOS single-channel 8- bit ADC compatible for energy-efficient high-speed Compressive Sensing (CS) and Nyquist Sampling (NS). A self-timed pipeline two-stage SAR-Binary-Search (BS) architecture is proposed and integrated with a 4GHz random-matrix clock generator, enabling a physical sampling speed up to 500MS/s with 40.2dB SNDR in NS-mode, and an equivalent speed up to 4GS/s with 36.2dB SNDR in CS-mode, leading to a FOM of 239fJ/conversion-step and 71fJ/conversion-step respectively. A Passive-charge-sharing (PCS) with open-loop (OL) residue-amplifier (RA) technique is proposed to boost the maximum physical sampling speed and the equivalent CS acquisition bandwidth. A reference-voltage fitting calibration scheme is applied to pre-distort inter-stage errors.

}, keywords = {psclab}, author = {Boyu Hu and Fengbo Ren and Zuow-Zun Chen and Xicheng Jiang and Mau-Chung Frank Chang} } @article {9999, title = {9-bit time{\textendash}digital-converter-assisted compressive-sensing analogue{\textendash}digital-converter with 4 GS/s equivalent speed}, journal = {IET Electronics Letters}, volume = {52}, year = {2016}, month = {03/2016}, pages = {430-432}, abstract = {

A novel 9-bit time{\textendash}digital-converter (TDC)-assisted analogue{\textendash}digital-converter (ADC) supporting energy-efficient high-speed compressive-sensing (CS) operation is presented. With a voltage{\textendash}time-converter serving as the cross-domain residue conveyer, the proposed two-stage self-timed pipeline ADC architecture hybrids a voltage-domain comparator-interleaved successive-approximation (SAR) ADC front-end and a time-domain locally readjusted folding two-dimensional Vernier TDC back-end. Implemented in 65 nm CMOS technology, the prototype benefits from both the CS-enabled sub-Nyquist operation and the hybrid quantisation scheme, leading up to 4 GS/s equivalent speed with 34.2 dB signal-noise-distortion-ratio (SNDR) and a figure-of-merit (FOM) of 101 fJ/conversion step.

}, keywords = {psclab}, author = {Boyu Hu and Fengbo Ren and Zuow-Zun Chen and Xicheng Jiang and Mau-Chung Frank Chang} } @inproceedings {2016, title = {A Binary Convolutional Encoder-decoder Network for Real-time Natural Scene Text Processing}, year = {2016}, month = {12/2016}, abstract = {

In this paper, we develop a binary convolutional encoder-decoder network (B-CEDNet) for natural scene text processing (NSTP). It converts a text image to a class-distinguished salience map that reveals the categorical, spatial and morphological information of characters. The existing solutions are either memory consuming or run-time consuming that cannot be applied to real-time applications on resource-constrained devices such as advanced driver assistance systems. The developed network can process multiple regions containing characters by one-off forward operation, and is trained to have binary weights and binary feature maps, which lead to both remarkable inference run-time speedup and memory usage reduction. By training with over 200, 000 synthesis scene text images (size of 32 \× 128), it can achieve 90\% and 91\% pixel-wise accuracy on ICDAR-03 and ICDAR-13 datasets. It only consumes 4.59 ms inference run-time realized on GPU with a small network size of 2.14 MB, which is up to 8\× faster and 96\% smaller than it full-precision version.\ 

}, keywords = {psclab}, author = {Liu, Zichuan and Yixing Li and Ren, Fengbo and Yu, Hao} } @inproceedings {104, title = {A Compressive-sensing based Testing Vehicle for 3D TSV Pre-bond and Post-bond Testing Data}, year = {2016}, month = {04/2016}, pages = {19-25}, abstract = {

Online testing vehicle is required for 3D TSV pre-bond and post-bond testing due to high probability of TSV failures. It has become a challenge to deal with large sets of generated testing data with limited probing when transmitting the data out. In this paper, a lossless compressive-sensing based testing vehicle is developed for online testing of TSVs. By exploring sparsity of the testing data under constraint of failure bound of TSV, sparse-representation based encoding can be deployed by XOR and AND network on chip to deal with large volume of testing data. Experimental results (with benchmarks) have shown that 89.70\% pre-bond data compression rate can be achieved under 0.5\% probability of failures; and 88.18\% post-bond data compression rate can be achieved with 5\% probability of failures.

}, keywords = {psclab}, author = {Hantao Huang and Hao Yu and Cheng Zhuo and Fengbo Ren} } @article {2015, title = {A Configurable 12{\textendash}237 kS/s 12.8 mW Sparse-Approximation Engine for Mobile Data Aggregation of Compressively Sampled Physiological Signals}, journal = {IEEE Journal of Solid-State Circuits}, volume = {51}, year = {2016}, month = {10/2015}, pages = {68-78}, abstract = {

Compressive sensing (CS) is a promising technology for realizing low-power and cost-effective wireless sensor nodes (WSNs) in pervasive health systems for 24/7 health monitoring. Due to the high computational complexity (CC) of the reconstruction algorithms, software solutions cannot fulfill the energy efficiency needs for real-time processing. In this paper, we present a 12\—237 kS/s 12.8 mW sparse-approximation (SA) engine chip that enables the energy-efficient data aggregation of compressively sampled physiological signals on mobile platforms. The SA engine chip integrated in 40 nm CMOS can support the simultaneous reconstruction of over 200 channels of physiological signals while consuming \<1\%of a smartphone\’s power budget. Such energy-efficient reconstruction enables two-to-three times energy saving at the sensor nodes in a CS-based health monitoring system as compared to traditional Nyquist-based systems, while providing timely feedback and bringing signal intelligence closer to the user.

}, keywords = {psclab}, url = {http://ieeexplore.ieee.org/xpl/login.jsp?tp=\&arnumber=7299281\&url=http\%3A\%2F\%2Fieeexplore.ieee.org\%2Fxpls\%2Fabs_all.jsp\%3Farnumber\%3D7299281}, author = {Ren, Fengbo and Markovi{\'c}, Dejan} } @inproceedings {9999, title = {An Energy-Efficient Compressive Sensing Framework Incorporating Online Dictionary Learning for Long-Term Wireless Health Monitoring}, year = {2016}, month = {03/2016}, pages = {804 - 808}, publisher = {IEEE}, address = {Shanghai, China}, abstract = {

Wireless body area network (WBAN) is emerging in the mobile healthcare area to replace the traditional wire-connected monitoring devices. As wireless data transmission dominates power cost of sensor nodes, it is beneficial to reduce the data size without much information loss. Compressive sensing (CS) is a perfect candidate to achieve this goal compared to existing compression techniques. In this paper, we proposed a general framework that utilize CS and online dictionary learning (ODL) together. The learned dictionary carries individual characteristics of the original signal, under which the signal has an even sparser representation compared to pre-determined dictionaries. As a consequence, the compression ratio is effectively improved by 2-4x comparing to prior works. Besides, the proposed framework offloads pre-processing from sensor nodes to the server node prior to dictionary learning, providing further reduction in hardware costs. As it is data driven, the proposed framework has the potential to be used with a wide range of physiological signals.

}, keywords = {psclab}, author = {Kai Xu and YIxing Li and Fengbo Ren} } @inproceedings {27, title = {A Configurable 12-to-237KS/s 12.8 mW Sparse-approximation Engine for Mobile ExG Data Aggregation}, year = {2015}, month = {Feb.}, pages = {68-78}, publisher = {IEEE}, abstract = {

Compressive sensing (CS) is a promising solution for low-power on-body sensors for 24/7 wireless health monitoring. In such an application, a mobile data aggregator performing real-time signal reconstruction is desired for timely prediction and proactive prevention. However, CS reconstruction requires solving a sparse approximation (SA) problem. Its high computational complexity makes software solvers, consuming 2-50W on CPUs, very energy inefficient for real-time processing. This paper presents a configurable SA engine in a 40nm CMOS technology for energy-efficient mobile data aggregation from compressively sampled biomedicai signals. Using configurable architecture, a 100\% utilization of computing resources is achieved. An efficient data-shuffling scheme is implemented to reduce memory leakage by 40\%. At the minimum-energy point (MEP), the SA engine achieves a real-time throughput for reconstructing 61-to-237 channels of biomedicai signals simultaneously with \<;1\% of a mobile device\&$\#$39;s 2W power budget, which is 76-350\× more energy-efficient than prior hardware designs.

}, keywords = {psclab}, url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7063062}, author = {Ren, Fengbo and Markovi{\'c}, Dejan} } @article {33, title = {Scalable and Parameterized VLSI Architecture for Compressive Sensing Sparse Approximation}, number = {US14/446,272}, year = {2015}, month = {Jan 29, 2015}, abstract = {

Systems and methods for implementing a scalable very-large-scale integration (VLSI) architecture to perform compressive sensing (CS) hardware reconstruction for data signals in accordance with embodiments of the invention are disclosed. The VLSI architecture is optimized for CS signal reconstruction by implementing a reformulation of the orthogonal matching pursuit (OMP) process and utilizing architecture resource sharing techniques. Typically, the VLSI architecture is a CS reconstruction engine that includes a vector and scalar computation cores where the cores can be time-multiplexed (via dynamic configuration) to perform each task associated with OMP. The vector core includes configurable processing elements (PEs) connected in parallel. Further, the cores can be linked by data-path memories, where complex data flow of OMP can be customized utilizing local memory controllers synchronized by a top-level finite-state machine. The computing resources (cores and data-paths) can be reused across the entire OMP process resulting in optimal utilization of the PEs.

}, keywords = {psclab}, issn = {US10073701B2}, url = {https://www.google.com/patents/US20150032990}, author = {Dejan Markovic and Fengbo Ren} } @mastersthesis {35, title = {A Scalable VLSI Architecture for Real-Time and Energy-Efficient Sparse Approximation in Compressive Sensing Systems}, volume = {Doctor of Philosophy}, year = {2015}, month = {Jan.}, school = {University of California, Los Angeles}, type = {Ph.D. Dissertation}, address = {Los Angeles}, abstract = {

Digital electronic industry today relies on Nyquist sampling theorem, which requires to double the size (sampling rate) of the signal representation on the Fourier basis to avoid information loss. However, most natural signals have very sparse representations on some other orthogonal (non-Fourier) basis. This mismatch implies a large redundancy in Nyquist-sampled data, making compression a necessity prior to storage or transmission. Recent advances in compressive sensing (CS) theory offer us an alternative data acquisition framework, which can greatly impact power-starved applications such as wireless sensors. CS techniques provide a universal approach to sample compressible signals at a rate significantly below the Nyquist rate with limited information loss. Therefore, CS is a promising technology for realizing configurable, cost-effective, miniaturized, and ultra-low-power data acquisition devices for mobile and wearable applications. However, the digital signal processing of compressively-sampled data involves solving a sparse approximation problem, which requires iterative-searching algorithms that have high computational complexity and require intensive memory access. As a result, existing software solutions are neither energy-efficient nor cost-effective for real-time processing of compressively-sampled data, especially when the processing is to be performed on energy-limited devices. To solve this problem, this dissertation presents a scalable VLSI architecture that can be implemented on field-programmable gate arrays (FPGAs) or system-on-chips (SoCs) to perform dedicated-hardware-driven sparse approximation. A VLSI soft-IP core of the sparse approximation engine is developed in Verilog-HDL, which supports a floating-point data format with 10 design parameters, providing a high dynamic range and the flexibility for application-specific user customizations. Taking advantage of the algorithm-architecture co-design that leverages algorithm reformulations, configurable architectures, and efficient memory mapping schemes, the proposed VLSI architecture features a 100\% utilization of the computing resources and is scalable in terms of computation parallelism and memory capability. The hardware emulation of the soft-IP core on a 28-nm Xilinx Kintex-7 FPGA shows that our design achieves the same level of accuracy as the double-precision C program running on an Intel Core i7-4700MQ mobile processor, while providing 47\–147x speed-up for ECG signal reconstruction. Furthermore, a 12\–237 KS/s 12.8 mW sparse approximation engine chip is realized in a 40-nm CMOS technology for enabling the mobile data aggregation of compressively sampled biomedical signals in CS-based wireless health monitoring systems. The measurement results show that the sparse approximation engine chip operating at the minimum energy point achieves a real-time throughput for reconstructing 61\–237 channels of biomedical signals simultaneously with \<1\% of a mobile device\&$\#$39;s 2W power budget, which is 14,100x more energy-efficient than the software solver running on the CPU. For high-sparsity signal reconstruction, the sparse approximation engine chip is 76\–350x more energy-efficient than prior hardware designs. With a \<1\% power budget of a mobile device, the 5.13 mm2 sparse approximation engine chip integrated in 40-nm CMOS can enable a 2\–3x energy saving at CS-based sensor nodes while providing timely feedback and bringing signal intelligence closer to the user, presenting a significant advantage for 24/7 wireless health monitoring.

}, keywords = {psclab}, author = {Ren, Fengbo} } @article {32, title = {Body Voltage Sensing Based Short Pulse Reading Circuit}, number = {PCT/US2012/056136}, year = {2014}, month = {Mar 28, 2013}, chapter = {WO2013043738A1}, abstract = {

As memory geometries continue to scale down, current density of magnetic tunnel junctions (MTJs) make conventional low current reading scheme problematic with regard to performance and reliability. A body-voltage sense circuit (BVSC) short pulse reading (SPR) circuit is described using body connected load transistors and a novel sensing circuit with second stage amplifier which allows for very short read pulses providing much higher read margins, less sensing time, and shorter sensing current pulses. Simulation results (using 65-nm CMOS model SPICE simulations) show that our technique can achieve 550 mV of read margin at 1 ns performance under a 1 V supply voltage, which is greater than reference designs achieve at 5 ns performance.

}, keywords = {psclab}, issn = {US8917562B2}, url = {http://www.google.com/patents/WO2013043738A1}, author = {Kang-Lung Wang and Chih-Kong K. Yang and Dejan Markovic and Fengbo Ren} } @article {19, title = {Healable Capacitive Touch Screen Sensors Based on Transparent Composite Electrodes Comprising Silver Nanowires and a Furan/Maleimide Diels-Alder Cycloaddition Polymer}, journal = {ACS Nano}, volume = {8}, year = {2014}, month = {Dec.}, pages = {12874{\textendash}12882}, abstract = {

A healable transparent capacitive touch screen sensor has been fabricated based on a healable silver nanowire{\textendash}polymer composite electrode. The composite electrode features a layer of silver nanowire percolation network embedded into the surface layer of a polymer substrate comprising an ultrathin soldering polymer layer to confine the nanowires to the surface of a healable Diels{\textendash}Alder cycloaddition copolymer and to attain low contact resistance between the nanowires. The composite electrode has a figure-of-merit sheet resistance of 18 Ω/sq with 80\% transmittance at 550 nm. A surface crack cut on the conductive surface with 18 Ω is healed by heating at 100 {\textdegree}C, and the sheet resistance recovers to 21 Ω in 6 min. A healable touch screen sensor with an array of 8 {\texttimes} 8 capacitive sensing points is prepared by stacking two composite films patterned with 8 rows and 8 columns of coupling electrodes at 90{\textdegree} angle. After deliberate damage, the coupling electrodes recover touch sensing function upon heating at 80 {\textdegree}C for 30 s. A capacitive touch screen based on Arduino is demonstrated capable of performing quick recovery from malfunction caused by a razor blade cutting. After four cycles of cutting and healing, the sensor array remains functional.

}, keywords = {psclab}, url = {http://pubs.acs.org/doi/abs/10.1021/nn506610p}, author = {Li, Junpeng and Liang, Jiajie and Li, Lu and Ren, Fengbo and Hu, Wei and Li, Juan and Qi, Shuhua and Pei, Qibing} } @inproceedings {23, title = {A Scalable Sparse Matrix-vector Multiplication Kernel for Energy-efficient Sparse-BLAS on FPGAs}, year = {2014}, month = {02/2014}, pages = {161-170}, publisher = {ACM}, abstract = {

Sparse Matrix-Vector Multiplication (SpMxV) is a widely used mathematical operation in many high-performance scientific and engineering applications. In recent years, tuned software libraries for multi-core microprocessors (CPUs) and graphics processing units (GPUs) have become the status quo for computing SpMxV. However, the computational throughput of these libraries for sparse matrices tends to be significantly lower than that of dense matrices, mostly due to the fact that the compression formats required to efficiently store sparse matrices mismatches traditional computing architectures. This paper describes an FPGA-based SpMxV kernel that is scalable to efficiently utilize the available memory bandwidth and computing resources. Benchmarking on a Virtex-5 SX95T FPGA demonstrates an average computational efficiency of 91.85\%. The kernel achieves a peak computational efficiency of 99.8\%, a \>50x improvement over two Intel Core i7 processors (i7-2600 and i7-4770) and showing a \>300x improvement over two NVIDA GPUs (GTX 660 and GTX Titan), when running the MKL and cuSPARSE sparse-BLAS libraries, respectively. In addition, the SpMxV FPGA kernel is able to achieve higher performance than its CPU and GPU counterparts, while using only 64 single-precision processing elements, with an overall 38-50x improvement in energy efficiency.

}, keywords = {psclab}, url = {http://dl.acm.org/citation.cfm?id=2554785}, author = {Dorrance, Richard and Ren, Fengbo and Markovi{\'c}, Dejan} } @article {22, title = {A Square-Root-Free Matrix Decomposition Method for Energy-Efficient Least Square Computation on Embedded Systems}, journal = {IEEE Embedded Systems Letters}, volume = {6}, year = {2014}, month = {Aug.}, pages = {73{\textendash}76}, abstract = {

QR decomposition (QRD) is used to solve least-squares (LS) problems for a wide range of applications. However, traditional QR decomposition methods, such as Gram-Schmidt (GS), require high computational complexity and nonlinear operations to achieve high throughput, limiting their usage on resource-limited platforms. To enable efficient LS computation on embedded systems for real-time applications, this paper presents an alternative decomposition method, called QDRD, which relaxes system requirements while maintaining the same level of performance. Specifically, QDRD eliminates both the square-root operations in the normalization step and the divisions in the subsequent backward substitution. Simulation results show that the accuracy and reliability of factorization matrices can be significantly improved by QDRD, especially when executed on precision-limited platforms. Furthermore, benchmarking results on an embedded platform show that QDRD provides constantly better energy-efficiency and higher throughput than GS-QRD in solving LS problems. Up to 4 and 6.5 times improvement in energy-efficiency and throughput, respectively, can be achieved for small-size problems.

}, keywords = {psclab}, url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6882128}, author = {Ren, Fengbo and Zhang, Chenxin and Liu, Liang and Xu, Wenyao and Owall, V and Markovi{\'c}, Dejan} } @article {17, title = {Statistical Timing and Power Analysis of VLSI Considering Non-linear Dependence}, journal = {the VLSI Journal Integration}, volume = {47}, year = {2014}, month = {Sep.}, pages = {487{\textendash}498}, abstract = {

Majority of practical multivariate statistical analysis and optimizations model interdependence among random variables in terms of the linear correlation. Though linear correlation is simple to use and evaluate, in several cases non-linear dependence between random variables may be too strong to ignore. In this paper, we propose polynomial correlation coefficients as simple measure of multi-variable non-linear dependence and show that the need for modeling non-linear dependence strongly depends on the end function that is to be evaluated from the random variables. Then, we calculate the errors in estimation resulting from assuming independence of components generated by linear de-correlation techniques, such as PCA and ICA. The experimental results show that the error predicted by our method is within 1\% error compared to the real simulation of statistical timing and leakage analysis. In order to deal with non-linear dependence, we further develop a target-function-driven component analysis algorithm (FCA) to minimize the error caused by ignoring high order dependence. We apply FCA to statistical leakage power analysis and SRAM cell noise margin variation analysis. Experimental results show that the proposed FCA method is more accurate compared to the traditional PCA or ICA.

}, keywords = {psclab}, url = {http://www.sciencedirect.com/science/article/pii/S0167926014000029}, author = {Cheng, Lerong and Xu, Wenyao and Ren, Fengbo and Gong, Fang and Gupta, Puneet and He, Lei} } @inproceedings {29, title = {mCOPD: Mobile Phone Based Lung Function Diagnosis and Exercise System for COPD}, year = {2013}, month = {05/2013}, publisher = {ACM}, abstract = {

COPD (Chronic Obstructive Pulmonary Disease) is a serious lung disease that causes difficulty in breathing. COPD patients require lung function examinations and perform breathing exercises on a regular basis in order to manage and be more aware of their health status. In this paper, we designed and developed a mobile-phone based system for lung function diagnosis, called mCOPD. Besides enabling accurate COPD examinations at home, the mCOPD system also offers a video-game based guidance system for breathing exercises. We evaluated mCOPD in controlled and uncontrolled environments with 40 subjects. The experimental results show that our system is a promising tool for remote medical treatment of COPD.

}, keywords = {psclab}, url = {http://dl.acm.org/citation.cfm?id=2504383}, author = {Xu, Wenyao and Huang, Ming-Chun and Liu, Jason J and Ren, Fengbo and Shen, Xinchen and Liu, Xiao and Sarrafzadeh, Majid} } @inproceedings {30, title = {Proper Running Posture Guide: A Wearable Biomechanics Capture System}, year = {2013}, month = {09/2013}, publisher = {ICST (Institute for Computer Sciences, Social-Informatics and Telecommunications Engineering)}, abstract = {

Running is a popular exercise for all age groups. It helps heart and lung functions, enhances muscle strength and control weight. Nevertheless, excessive fatigue and severe injury resulting from inappropriate running poses might reduce the benefits brought by this exercise and stop people from keeping running regularly. In this paper, we design a system that can monitor the running biomechanics, infer running poses, analyze running patterns, and provide both real-time and off-line feedbacks to reduce unnecessary fatigue and unwanted injuries. Common inappropriate running patterns, over-striding, over-pronating and out-sync, are identified and analyzed with the continuous wearable sensor data streams. Two types of correctional feedbacks are designed to provide users appropriate adjustment guidance: vibrating the areas of user body where improper poses are detected and visualizing running video with sensor waveforms to indicate which inappropriate motions trigger the vibration. With reasonable adjustment, running can be a safe and effective activity for a healthy lifestyle.

}, keywords = {psclab}, url = {http://dl.acm.org/citation.cfm?id=2555333}, author = {Zhang, Xiaoyi and Huang, Ming-Chun and Ren, Fengbo and Xu, Wenyao and Guan, Nan and Yi, Wang} } @article {20, title = {Reference Calibration of Body-voltage Sensing Circuit for High-speed STT-RAMs}, journal = {IEEE Transactions on Circuits and Systems I: Regular Papers}, volume = {60}, year = {2013}, month = {Apr.}, pages = {2932{\textendash}2939}, abstract = {

With the continuing scaling of MTJ, the high-speed reading of STT-RAM becomes increasingly difficult. Recently, a body-voltage sensing circuit (BVSC) has been proposed for boosting the sensing speed. This paper analyzes the effectiveness of using the reference calibration technique to compensate for the device mismatches and improve the read margin of BVSC. HSPICE simulation results show that a 2-bit reference calibration can improve the worst-case read margin in a 1-Mb memory by over 3 times. This leads to up to 30\% higher yield across all process corners. In order to maintain the yield improvement even in the worst-case corner, independent calibration circuitry has to be deployed for each memory array.

}, keywords = {psclab}, url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6492140}, author = {Ren, Fengbo and Park, Henry and Yang, C-KK and Markovi{\'c}, Dejan} } @article {21, title = {Scalable and Parameterised VLSI Architecture for Efficient Sparse Approximation in FPGAs And SoCs}, journal = {IET Electronics Letters}, volume = {49}, year = {2013}, month = {Nov.}, pages = {1440{\textendash}1441}, abstract = {

A parameterised and scalable very large scale integration (VLSI) soft intellectual property (IP) is presented that can be implemented in programmable logic devices, such as field programmable gate arrays (FPGAs) or a system-on-chip design for efficient sparse approximation. The proposed architecture is optimised based on the orthogonal matching pursuit algorithm by both algorithm reformulation and architecture resource sharing techniques. The soft IP core supports a floating-point data format with 10 design parameters, which provides the necessary flexibility for application-specific customisation. The soft IP is evaluated on various FPGA platforms. The evaluation results show that design can achieve up to 30\% higher throughput than the existing solutions while offering a larger dynamic range capability and better design flexibility.

}, keywords = {psclab}, url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6675715}, author = {Ren, Fengbo and Xu, Wenyao and Markovi{\'c}, Dejan} } @inproceedings {31, title = {See UV on Your Skin: An Ultraviolet Sensing and Visualization System}, year = {2013}, month = {09/2013}, pages = {22-28}, publisher = {ICST (Institute for Computer Sciences, Social-Informatics and Telecommunications Engineering)}, abstract = {

These days, as the Earth{\textquoteright}s protective ozone layer gets thinner, ultraviolet (UV) radiation threat is growing. In addition, getting tanned as a fashion leads people to wear less clothing, which increases UV intake. Excessive exposure to ultraviolet will lead to sunburn and even skin cancer. Therefore, neither insufficient nor excessive exposure is desirable. Although there are tons of UV meters on the market, a user may have a hard time to understand the unintuitive UV index reading. Thus, there is a potential demand for a portable system which can keep track of daily UV exposure dose, visualize possible sunburned consequences, and provide appropriate skin care recommendations. In this paper, we present a personalized UV monitoring and notification system. This system can continuously track UV exposure by wearable UV sensors. It can also visualize the cumulative UV exposure dose according to a predictive sunburned skin color model. Such an augmented skin color can provide a warning message to indicate the possible result of continuous UV exposure. Compared with other existing systems, our solution not only allows users to monitor their daily UV exposure, but also provides an unobtrusive UV visualization model which effectively warns users to take appropriate actions to avoid potential skin damage. The system has been tested on 9 subjects, and the evaluation feedback indicates that our system is promising for UV monitoring and sunburn prevention.

}, keywords = {psclab}, url = {http://dl.acm.org/citation.cfm?id=2555324}, author = {Zhang, Xiaoyi and Xu, Wenyao and Huang, Ming-Chun and Amini, Navid and Ren, Fengbo} } @inproceedings {26, title = {A Single-precision Compressive Sensing Signal Reconstruction Engine on FPGAs}, year = {2013}, month = {09/2013}, pages = {1-4}, publisher = {IEEE}, abstract = {

Compressive sensing (CS) is a promising technology for the low-power and cost-effective data acquisition in wireless healthcare systems. However, its efficient realtime signal reconstruction is still challenging, and there is a clear demand for hardware acceleration. In this paper, we present the first single-precision floating-point CS reconstruction engine implemented a Kintex-7 FPGA using the orthogonal matching pursuit (OMP) algorithm. In order to achieve high performance with maximum hardware utilization, we propose a highly parallel architecture that shares the computing resources among different tasks of OMP by using configurable processing elements (PEs). By fully utilizing the FPGA recourses, our implementation has 128 PEs in parallel and operates at 53.7 MHz. In addition, it can support 2x larger problem size and 10x more sparse coefficients than prior work, which enables higher reconstruction accuracy by adding finer details to the recovered signal. Hardware results from the ECG reconstruction tests show the same level of accuracy as the double-precision C program. Compared to the execution time of a 2.27 GHz CPU, the FPGA reconstruction achieves an average speed-up of 41x.

}, keywords = {psclab}, url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6645574}, author = {Ren, Fengbo and Dorrace, Richard and Xu, Wenyao and Markovi{\'c}, Dejan} } @inproceedings {28, title = {A Body-voltage-sensing-based Short Pulse Reading Circuit for Spin-torque Transfer RAMs (STT-RAMs)}, year = {2012}, month = {03/2012}, pages = {275-282}, publisher = {IEEE}, abstract = {

With scaling of CMOS and Magnetic Tunnel Junction (MTJ) devices, conventional low-current reading techniques for STT-RAMs face challenges in achieving reliability and performance improvements that are expected from scaled devices. The challenges arise from the increasing variability of the CMOS sensing current and the reduction in MTJ switching current. This paper proposes a short-pulse reading circuit, based on a body-voltage sensing scheme to mitigate the scaling issues. Compared to existing sensing techniques, our technique shows substantially higher read margin (RM) despite a much shorter sensing time. A narrow current pulse applied to an MTJ significantly reduces the probability of read disturbance. The RM analysis is validated by Monte-Carlo simulations in a 65-nm CMOS technology with both CMOS and MTJ variations considered. Simulation results show that our technique is able to provide over 300 mV RM at a GHz frequency across process-voltage-temperature (PVT) variations, while the reference designs require 4.3 ns and 2.3 ns sensing time for a 200 mV RM, respectively. The effective read energy per bit required by the proposed sensing circuit is around 195 ft in the nominal case.

}, keywords = {psclab}, url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6187506}, author = {Ren, Fengbo and Park, Henry and Dorrance, Richard and Toriyama, Yuta and Yang, C-KK and Markovi{\'c}, Dejan} } @article {18, title = {Scalability and Design-space Analysis of A 1T-1MTJ Memory Cell For STT-RAMs}, journal = {IEEE Transactions on Electron Devices}, volume = {59}, year = {2012}, month = {Jan.}, pages = {878{\textendash}887}, abstract = {

We present a design-space feasibility region, as a function of magnetic tunnel junction (MTJ) characteristics and target memory specifications, to explore the design margin of a one-transistor-one-magnetic-tunnel-junction (1T-1MTJ) memory cell for spin-transfer torque random access memories (STT-RAMs). Data from measured devices are used to model the statistical variation of an MTJ{\textquoteright}s critical switching current and resistance. The sensitivity of the design space to different design parameters is also analyzed for the scaling of both the MTJ and the underlying transistor technology. A design flow, using a sensitivity-based analysis and an MTJ switching model based on the Landau-Lifshitz-Gilbert equation, is proposed to optimize design margins for gigabit-scale memories. Design points for improved yield, density, and memory performance are extracted from MTJ-compatible complementary metal-oxide-semiconductor (CMOS) technologies for 90-, 65-, 45-, and 32-nm processes. Predictive technology models are used to explore the future scalability of STT-RAMs in upcoming 22- and 16-nm technology nodes. Our analysis shows that, to achieve Flash-like densities ( \<; 6F2) in advanced CMOS technologies, aggressive scaling of the critical switching current density will be required.

}, keywords = {psclab}, url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6140952}, author = {Dorrance, Richard and Ren, Fengbo and Toriyama, Yuta and Hafez, Amr Amin and Yang, C-KK and Markovi{\'c}, Dejan} } @inproceedings {25, title = {Analysis of STT-RAM Cell Design With Multiple MTJs Per Access}, year = {2011}, month = {01/2011}, pages = {53-58}, publisher = {IEEE Computer Society}, abstract = {

Density of STT-RAMs is limited by the area cost and width of the access device in a cell since it needs to support the programming currents. This paper explores a cell structure that shares each cell{\textquoteright}s access transistor with multiple MTJ memory elements. Feasibility and limitations of such a cell structure is explored for both reading and writing of the memory. The analytical and simulation results indicate that only small amount of sharing is possible and having MTJs that can handle a high read current without disturbing the cell is needed.

}, keywords = {psclab}, url = {http://dl.acm.org/citation.cfm?id=2052103}, author = {Park, Henry and Dorrance, Richard and Amin, Amr and Ren, Fengbo and Markovi{\'c}, Dejan and Ken Yang, CK} } @mastersthesis {34, title = {Energy-performance Characterization of CMOS/Magnetic Tunnel Junction (MTJ) Hybrid Logic Circuits}, volume = {Master of Science }, year = {2011}, month = {Jan. 2011}, school = {University of California, Los Angeles}, type = {M.S. Thesis}, address = {Los Angeles}, abstract = {

Magnetic Tunnel Junction (MTJ) devices are CMOS compatible with high stability, high reliability and non-volatility. All these features are promising for building non-volatile CMOS/MTJ hybrid logic circuits that do not consume off-state leakage current and that supports ultra-low-power operation. However, most existing proposals for this purpose so far lack an energy-performance analysis and a comparison to CMOS circuits. In this work, we analyze and compare the energy-performance characteristics of a wide range of CMOS/MTJ hybrid circuits over the device, circuit and architectural levels. This will include device switching energies, logic-in-memory MTJ (LIM-MTJ) logic circuit, two MTJ reading circuits and two CMOS/MTJ hybrid lookup table (LUT) architectures. Our analysis shows that the existing LIM-MTJ logic style has no advantage in energy-performance over its equivalent CMOS design, and that with the switching energy of MTJ considered, the CMOS/MTJ hybrid circuit requiring frequent MTJ switching is hardly energy efficient. Our simulation results also show that the cross-coupled inverter based MTJ reading circuit has 4 times greater performance and 30 times lower energy than the current-mirror sense amplifier based reading circuit. It is also shown that the proposed CMOS/MTJ hybrid LUT based logic architecture, which requires no MTJ switching during logic operations, is able to incorporate the non-volatility of the MTJ to alleviate the leakage problem of CMOS, and to thereby supports ultra-low power operation in advanced technology nodes (32-nm and beyond).

}, keywords = {psclab}, author = {Ren, Fengbo} } @inproceedings {24, title = {Scalability And Design-space Analysis of A 1T-1MTJ Memory Cell}, year = {2011}, month = {01/2011}, pages = {32-36}, publisher = {IEEE}, abstract = {

This paper introduces a design-space feasibility region as a function of MTJ characteristics and memory target specifications. The sensitivity of the design space is analyzed for scaling of both MTJ and underlying transistor technology. Design points for improved yield, density, and memory performance can be extracted for 90nm down to 32nm processes based on measured MTJ devices. To achieve flash-like densities in upcoming 22nm and 16nm technology nodes, scaling of the critical switching current density is required.

}, keywords = {psclab}, url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5941480}, author = {Dorrance, Richard and Ren, Fengbo and Toriyama, Yuta and Amin, Amr and Yang, C-KK and Markovi{\'c}, Dejan} } @article {16, title = {True Energy-performance Analysis Of The MTJ-based Logic-in-memory Architecture (1-bit Full Adder)}, journal = {IEEE Transactions on Electron Devices}, volume = {57}, year = {2010}, month = {Mar.}, pages = {1023{\textendash}1028}, abstract = {

The use of spin-transfer torque (STT) devices for memory design has been a subject of research since the discovery of the STT on MgO-based magnetic tunnel junctions (MTJs). Recently, MTJ-based computing architectures such as logic-in-memory have been proposed and claim superior energy-delay performance over static CMOS. In this paper, we conduct exhaustive energy-performance analysis of an STT-MTJ-based logic-in-memory (LIM-MTJ) 1-bit full adder and compare it with its corresponding CMOS counterpart. Our results show that the LIM-MTJ circuit has no advantage in energy-performance over its equivalent CMOS designs. We also show that the MTJ-based logic circuit requiring frequent MTJ switching during the operation is hardly power efficient.

}, keywords = {psclab}, url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5437290\&tag=1}, author = {Ren, Fengbo and Markovi{\'c}, Dejan} }