@inproceedings {London, UK, title = {STPLS3D: A Large-Scale Synthetic and Real Aerial Photogrammetry 3D Point Cloud Dataset}, year = {2022}, month = {11/2022}, address = {London, UK}, abstract = {

Although various 3D datasets with different functions and scales have been proposed recently, it remains challenging for individuals to complete the whole pipeline of large- scale data collection, sanitization, and annotation. Moreover, the created datasets usually face the challenge of extremely imbalanced class distribution or partial low-quality data samples. Motivated by this, we explore the procedurally synthetic 3D data generation paradigm to equip individuals with the full capability of creating large-scale annotated photogrammetry point clouds. Specifically, we introduce a synthetic aerial photogrammetry point clouds generation pipeline that takes full advantage of open geospatial data sources and off-the-shelf commercial packages. Unlike generating synthetic data in virtual games, where the simulated data usually have limited gaming environments created by artists, the proposed pipeline simulates the reconstruction process of the real environment by following the same UAV flight pattern on different synthetic terrain shapes and building densities, which ensure similar quality, noise pattern, and diversity with real data. In addition, the precise semantic and instance annotations can be generated fully automatically, avoiding the expensive and time-consuming manual annotation. Based on\ the proposed pipeline, we present a richly-annotated synthetic 3D aerial photogrammetry point cloud dataset, termed STPLS3D, with more than 16 km2 of landscapes and up to 18 fine-grained semantic categories. For verification purposes, we also provide datasets collected from four areas in the real environment. Extensive experiments conducted on our datasets demonstrate the effectiveness and quality of the proposed synthetic dataset.

}, keywords = {psclab}, url = {https://www.stpls3d.com/}, author = {Meida Chen and Qingyong Hu and Zifan Yu and Hugues Thomas and Andrew Feng and Yu Hou and Kyle McCullough and Fengbo Ren and Lucio Soibelman} } @article {561, title = {OpenICS: Open Image Compressive Sensing Toolbox and Benchmark}, journal = {Software Impacts}, volume = {9}, year = {2021}, month = {05/2021}, abstract = {

The real-world application of image compressive sensing is largely limited by the lack of standardization in implementation and evaluation. To address this limitation, we present OpenICS, an image compressive sensing toolbox that implements multiple popular image compressive sensing algorithms into a unified framework with a standardized user interface. Furthermore, a corresponding benchmark is also proposed to provide a fair and complete evaluation of the implemented algorithms. We hope this work can serve the growing research community of compressive sensing and the industry to facilitate the development and application of image compressive sensing.

}, keywords = {psclab}, doi = {https://doi.org/10.1016/j.simpa.2021.100081}, url = {https://arxiv.org/pdf/2103.00652.pdf}, author = {Jonathan Zhao and Matthew Westerham and Mark Lakatos-Toth and Zhikang Zhang and Avi Moskoff and Fengbo Ren} } @mastersthesis {410, title = {Hardware Acceleration of Most Apparent Distortion Image Quality Assessment Algorithm on FPGA Using OpenCL}, year = {2017}, school = {Arizona State University}, type = {Master Thesis}, abstract = {

The information era has brought about many technological advancements in the past few decades, and that has led to an exponential increase in the creation of digital images and videos. Constantly, all digital images go through some image processing algorithm for various reasons like compression, transmission, storage, etc. There is data loss during this process which leaves us with a degraded image. Hence, to ensure minimal degradation of images, the requirement for quality assessment has become mandatory. Image Quality Assessment (IQA) has been researched and developed over the last several decades to predict the quality score in a manner that agrees with human judgments of quality. Modern image quality assessment (IQA) algorithms are quite effective at prediction accuracy, and their development has not focused on improving computational performance. The existing serial implementation requires a relatively large run-time on the order of seconds for a single frame. Hardware acceleration using Field programmable gate arrays (FPGAs) provides reconfigurable computing fabric that can be tailored for a broad range of applications. Usually, programming FPGAs has required expertise in hardware descriptive languages (HDLs) or high-level synthesis (HLS) tool. OpenCL is an open standard for cross-platform, parallel programming of heterogeneous systems along with Altera OpenCL SDK, enabling developers to use FPGA\&$\#$39;s potential without extensive hardware knowledge. Hence, this thesis focuses on accelerating the computationally intensive part of the most apparent distortion (MAD) algorithm on FPGA using OpenCL. The results are compared with CPU implementation to evaluate performance and efficiency gains.

}, keywords = {psclab}, author = {Aswin Gunavelu Mohan} } @article {2015, title = {A Configurable 12{\textendash}237 kS/s 12.8 mW Sparse-Approximation Engine for Mobile Data Aggregation of Compressively Sampled Physiological Signals}, journal = {IEEE Journal of Solid-State Circuits}, volume = {51}, year = {2016}, month = {10/2015}, pages = {68-78}, abstract = {

Compressive sensing (CS) is a promising technology for realizing low-power and cost-effective wireless sensor nodes (WSNs) in pervasive health systems for 24/7 health monitoring. Due to the high computational complexity (CC) of the reconstruction algorithms, software solutions cannot fulfill the energy efficiency needs for real-time processing. In this paper, we present a 12\—237 kS/s 12.8 mW sparse-approximation (SA) engine chip that enables the energy-efficient data aggregation of compressively sampled physiological signals on mobile platforms. The SA engine chip integrated in 40 nm CMOS can support the simultaneous reconstruction of over 200 channels of physiological signals while consuming \<1\%of a smartphone\’s power budget. Such energy-efficient reconstruction enables two-to-three times energy saving at the sensor nodes in a CS-based health monitoring system as compared to traditional Nyquist-based systems, while providing timely feedback and bringing signal intelligence closer to the user.

}, keywords = {psclab}, url = {http://ieeexplore.ieee.org/xpl/login.jsp?tp=\&arnumber=7299281\&url=http\%3A\%2F\%2Fieeexplore.ieee.org\%2Fxpls\%2Fabs_all.jsp\%3Farnumber\%3D7299281}, author = {Ren, Fengbo and Markovi{\'c}, Dejan} } @inproceedings {27, title = {A Configurable 12-to-237KS/s 12.8 mW Sparse-approximation Engine for Mobile ExG Data Aggregation}, year = {2015}, month = {Feb.}, pages = {68-78}, publisher = {IEEE}, abstract = {

Compressive sensing (CS) is a promising solution for low-power on-body sensors for 24/7 wireless health monitoring. In such an application, a mobile data aggregator performing real-time signal reconstruction is desired for timely prediction and proactive prevention. However, CS reconstruction requires solving a sparse approximation (SA) problem. Its high computational complexity makes software solvers, consuming 2-50W on CPUs, very energy inefficient for real-time processing. This paper presents a configurable SA engine in a 40nm CMOS technology for energy-efficient mobile data aggregation from compressively sampled biomedicai signals. Using configurable architecture, a 100\% utilization of computing resources is achieved. An efficient data-shuffling scheme is implemented to reduce memory leakage by 40\%. At the minimum-energy point (MEP), the SA engine achieves a real-time throughput for reconstructing 61-to-237 channels of biomedicai signals simultaneously with \<;1\% of a mobile device\&$\#$39;s 2W power budget, which is 76-350\× more energy-efficient than prior hardware designs.

}, keywords = {psclab}, url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=7063062}, author = {Ren, Fengbo and Markovi{\'c}, Dejan} } @article {33, title = {Scalable and Parameterized VLSI Architecture for Compressive Sensing Sparse Approximation}, number = {US14/446,272}, year = {2015}, month = {Jan 29, 2015}, abstract = {

Systems and methods for implementing a scalable very-large-scale integration (VLSI) architecture to perform compressive sensing (CS) hardware reconstruction for data signals in accordance with embodiments of the invention are disclosed. The VLSI architecture is optimized for CS signal reconstruction by implementing a reformulation of the orthogonal matching pursuit (OMP) process and utilizing architecture resource sharing techniques. Typically, the VLSI architecture is a CS reconstruction engine that includes a vector and scalar computation cores where the cores can be time-multiplexed (via dynamic configuration) to perform each task associated with OMP. The vector core includes configurable processing elements (PEs) connected in parallel. Further, the cores can be linked by data-path memories, where complex data flow of OMP can be customized utilizing local memory controllers synchronized by a top-level finite-state machine. The computing resources (cores and data-paths) can be reused across the entire OMP process resulting in optimal utilization of the PEs.

}, keywords = {psclab}, issn = {US10073701B2}, url = {https://www.google.com/patents/US20150032990}, author = {Dejan Markovic and Fengbo Ren} } @article {32, title = {Body Voltage Sensing Based Short Pulse Reading Circuit}, number = {PCT/US2012/056136}, year = {2014}, month = {Mar 28, 2013}, chapter = {WO2013043738A1}, abstract = {

As memory geometries continue to scale down, current density of magnetic tunnel junctions (MTJs) make conventional low current reading scheme problematic with regard to performance and reliability. A body-voltage sense circuit (BVSC) short pulse reading (SPR) circuit is described using body connected load transistors and a novel sensing circuit with second stage amplifier which allows for very short read pulses providing much higher read margins, less sensing time, and shorter sensing current pulses. Simulation results (using 65-nm CMOS model SPICE simulations) show that our technique can achieve 550 mV of read margin at 1 ns performance under a 1 V supply voltage, which is greater than reference designs achieve at 5 ns performance.

}, keywords = {psclab}, issn = {US8917562B2}, url = {http://www.google.com/patents/WO2013043738A1}, author = {Kang-Lung Wang and Chih-Kong K. Yang and Dejan Markovic and Fengbo Ren} } @inproceedings {23, title = {A Scalable Sparse Matrix-vector Multiplication Kernel for Energy-efficient Sparse-BLAS on FPGAs}, year = {2014}, month = {02/2014}, pages = {161-170}, publisher = {ACM}, abstract = {

Sparse Matrix-Vector Multiplication (SpMxV) is a widely used mathematical operation in many high-performance scientific and engineering applications. In recent years, tuned software libraries for multi-core microprocessors (CPUs) and graphics processing units (GPUs) have become the status quo for computing SpMxV. However, the computational throughput of these libraries for sparse matrices tends to be significantly lower than that of dense matrices, mostly due to the fact that the compression formats required to efficiently store sparse matrices mismatches traditional computing architectures. This paper describes an FPGA-based SpMxV kernel that is scalable to efficiently utilize the available memory bandwidth and computing resources. Benchmarking on a Virtex-5 SX95T FPGA demonstrates an average computational efficiency of 91.85\%. The kernel achieves a peak computational efficiency of 99.8\%, a \>50x improvement over two Intel Core i7 processors (i7-2600 and i7-4770) and showing a \>300x improvement over two NVIDA GPUs (GTX 660 and GTX Titan), when running the MKL and cuSPARSE sparse-BLAS libraries, respectively. In addition, the SpMxV FPGA kernel is able to achieve higher performance than its CPU and GPU counterparts, while using only 64 single-precision processing elements, with an overall 38-50x improvement in energy efficiency.

}, keywords = {psclab}, url = {http://dl.acm.org/citation.cfm?id=2554785}, author = {Dorrance, Richard and Ren, Fengbo and Markovi{\'c}, Dejan} } @article {22, title = {A Square-Root-Free Matrix Decomposition Method for Energy-Efficient Least Square Computation on Embedded Systems}, journal = {IEEE Embedded Systems Letters}, volume = {6}, year = {2014}, month = {Aug.}, pages = {73{\textendash}76}, abstract = {

QR decomposition (QRD) is used to solve least-squares (LS) problems for a wide range of applications. However, traditional QR decomposition methods, such as Gram-Schmidt (GS), require high computational complexity and nonlinear operations to achieve high throughput, limiting their usage on resource-limited platforms. To enable efficient LS computation on embedded systems for real-time applications, this paper presents an alternative decomposition method, called QDRD, which relaxes system requirements while maintaining the same level of performance. Specifically, QDRD eliminates both the square-root operations in the normalization step and the divisions in the subsequent backward substitution. Simulation results show that the accuracy and reliability of factorization matrices can be significantly improved by QDRD, especially when executed on precision-limited platforms. Furthermore, benchmarking results on an embedded platform show that QDRD provides constantly better energy-efficiency and higher throughput than GS-QRD in solving LS problems. Up to 4 and 6.5 times improvement in energy-efficiency and throughput, respectively, can be achieved for small-size problems.

}, keywords = {psclab}, url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6882128}, author = {Ren, Fengbo and Zhang, Chenxin and Liu, Liang and Xu, Wenyao and Owall, V and Markovi{\'c}, Dejan} } @article {20, title = {Reference Calibration of Body-voltage Sensing Circuit for High-speed STT-RAMs}, journal = {IEEE Transactions on Circuits and Systems I: Regular Papers}, volume = {60}, year = {2013}, month = {Apr.}, pages = {2932{\textendash}2939}, abstract = {

With the continuing scaling of MTJ, the high-speed reading of STT-RAM becomes increasingly difficult. Recently, a body-voltage sensing circuit (BVSC) has been proposed for boosting the sensing speed. This paper analyzes the effectiveness of using the reference calibration technique to compensate for the device mismatches and improve the read margin of BVSC. HSPICE simulation results show that a 2-bit reference calibration can improve the worst-case read margin in a 1-Mb memory by over 3 times. This leads to up to 30\% higher yield across all process corners. In order to maintain the yield improvement even in the worst-case corner, independent calibration circuitry has to be deployed for each memory array.

}, keywords = {psclab}, url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6492140}, author = {Ren, Fengbo and Park, Henry and Yang, C-KK and Markovi{\'c}, Dejan} } @article {21, title = {Scalable and Parameterised VLSI Architecture for Efficient Sparse Approximation in FPGAs And SoCs}, journal = {IET Electronics Letters}, volume = {49}, year = {2013}, month = {Nov.}, pages = {1440{\textendash}1441}, abstract = {

A parameterised and scalable very large scale integration (VLSI) soft intellectual property (IP) is presented that can be implemented in programmable logic devices, such as field programmable gate arrays (FPGAs) or a system-on-chip design for efficient sparse approximation. The proposed architecture is optimised based on the orthogonal matching pursuit algorithm by both algorithm reformulation and architecture resource sharing techniques. The soft IP core supports a floating-point data format with 10 design parameters, which provides the necessary flexibility for application-specific customisation. The soft IP is evaluated on various FPGA platforms. The evaluation results show that design can achieve up to 30\% higher throughput than the existing solutions while offering a larger dynamic range capability and better design flexibility.

}, keywords = {psclab}, url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6675715}, author = {Ren, Fengbo and Xu, Wenyao and Markovi{\'c}, Dejan} } @inproceedings {26, title = {A Single-precision Compressive Sensing Signal Reconstruction Engine on FPGAs}, year = {2013}, month = {09/2013}, pages = {1-4}, publisher = {IEEE}, abstract = {

Compressive sensing (CS) is a promising technology for the low-power and cost-effective data acquisition in wireless healthcare systems. However, its efficient realtime signal reconstruction is still challenging, and there is a clear demand for hardware acceleration. In this paper, we present the first single-precision floating-point CS reconstruction engine implemented a Kintex-7 FPGA using the orthogonal matching pursuit (OMP) algorithm. In order to achieve high performance with maximum hardware utilization, we propose a highly parallel architecture that shares the computing resources among different tasks of OMP by using configurable processing elements (PEs). By fully utilizing the FPGA recourses, our implementation has 128 PEs in parallel and operates at 53.7 MHz. In addition, it can support 2x larger problem size and 10x more sparse coefficients than prior work, which enables higher reconstruction accuracy by adding finer details to the recovered signal. Hardware results from the ECG reconstruction tests show the same level of accuracy as the double-precision C program. Compared to the execution time of a 2.27 GHz CPU, the FPGA reconstruction achieves an average speed-up of 41x.

}, keywords = {psclab}, url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6645574}, author = {Ren, Fengbo and Dorrace, Richard and Xu, Wenyao and Markovi{\'c}, Dejan} } @inproceedings {28, title = {A Body-voltage-sensing-based Short Pulse Reading Circuit for Spin-torque Transfer RAMs (STT-RAMs)}, year = {2012}, month = {03/2012}, pages = {275-282}, publisher = {IEEE}, abstract = {

With scaling of CMOS and Magnetic Tunnel Junction (MTJ) devices, conventional low-current reading techniques for STT-RAMs face challenges in achieving reliability and performance improvements that are expected from scaled devices. The challenges arise from the increasing variability of the CMOS sensing current and the reduction in MTJ switching current. This paper proposes a short-pulse reading circuit, based on a body-voltage sensing scheme to mitigate the scaling issues. Compared to existing sensing techniques, our technique shows substantially higher read margin (RM) despite a much shorter sensing time. A narrow current pulse applied to an MTJ significantly reduces the probability of read disturbance. The RM analysis is validated by Monte-Carlo simulations in a 65-nm CMOS technology with both CMOS and MTJ variations considered. Simulation results show that our technique is able to provide over 300 mV RM at a GHz frequency across process-voltage-temperature (PVT) variations, while the reference designs require 4.3 ns and 2.3 ns sensing time for a 200 mV RM, respectively. The effective read energy per bit required by the proposed sensing circuit is around 195 ft in the nominal case.

}, keywords = {psclab}, url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6187506}, author = {Ren, Fengbo and Park, Henry and Dorrance, Richard and Toriyama, Yuta and Yang, C-KK and Markovi{\'c}, Dejan} } @article {18, title = {Scalability and Design-space Analysis of A 1T-1MTJ Memory Cell For STT-RAMs}, journal = {IEEE Transactions on Electron Devices}, volume = {59}, year = {2012}, month = {Jan.}, pages = {878{\textendash}887}, abstract = {

We present a design-space feasibility region, as a function of magnetic tunnel junction (MTJ) characteristics and target memory specifications, to explore the design margin of a one-transistor-one-magnetic-tunnel-junction (1T-1MTJ) memory cell for spin-transfer torque random access memories (STT-RAMs). Data from measured devices are used to model the statistical variation of an MTJ{\textquoteright}s critical switching current and resistance. The sensitivity of the design space to different design parameters is also analyzed for the scaling of both the MTJ and the underlying transistor technology. A design flow, using a sensitivity-based analysis and an MTJ switching model based on the Landau-Lifshitz-Gilbert equation, is proposed to optimize design margins for gigabit-scale memories. Design points for improved yield, density, and memory performance are extracted from MTJ-compatible complementary metal-oxide-semiconductor (CMOS) technologies for 90-, 65-, 45-, and 32-nm processes. Predictive technology models are used to explore the future scalability of STT-RAMs in upcoming 22- and 16-nm technology nodes. Our analysis shows that, to achieve Flash-like densities ( \<; 6F2) in advanced CMOS technologies, aggressive scaling of the critical switching current density will be required.

}, keywords = {psclab}, url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6140952}, author = {Dorrance, Richard and Ren, Fengbo and Toriyama, Yuta and Hafez, Amr Amin and Yang, C-KK and Markovi{\'c}, Dejan} } @inproceedings {25, title = {Analysis of STT-RAM Cell Design With Multiple MTJs Per Access}, year = {2011}, month = {01/2011}, pages = {53-58}, publisher = {IEEE Computer Society}, abstract = {

Density of STT-RAMs is limited by the area cost and width of the access device in a cell since it needs to support the programming currents. This paper explores a cell structure that shares each cell{\textquoteright}s access transistor with multiple MTJ memory elements. Feasibility and limitations of such a cell structure is explored for both reading and writing of the memory. The analytical and simulation results indicate that only small amount of sharing is possible and having MTJs that can handle a high read current without disturbing the cell is needed.

}, keywords = {psclab}, url = {http://dl.acm.org/citation.cfm?id=2052103}, author = {Park, Henry and Dorrance, Richard and Amin, Amr and Ren, Fengbo and Markovi{\'c}, Dejan and Ken Yang, CK} } @inproceedings {24, title = {Scalability And Design-space Analysis of A 1T-1MTJ Memory Cell}, year = {2011}, month = {01/2011}, pages = {32-36}, publisher = {IEEE}, abstract = {

This paper introduces a design-space feasibility region as a function of MTJ characteristics and memory target specifications. The sensitivity of the design space is analyzed for scaling of both MTJ and underlying transistor technology. Design points for improved yield, density, and memory performance can be extracted for 90nm down to 32nm processes based on measured MTJ devices. To achieve flash-like densities in upcoming 22nm and 16nm technology nodes, scaling of the critical switching current density is required.

}, keywords = {psclab}, url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5941480}, author = {Dorrance, Richard and Ren, Fengbo and Toriyama, Yuta and Amin, Amr and Yang, C-KK and Markovi{\'c}, Dejan} } @article {16, title = {True Energy-performance Analysis Of The MTJ-based Logic-in-memory Architecture (1-bit Full Adder)}, journal = {IEEE Transactions on Electron Devices}, volume = {57}, year = {2010}, month = {Mar.}, pages = {1023{\textendash}1028}, abstract = {

The use of spin-transfer torque (STT) devices for memory design has been a subject of research since the discovery of the STT on MgO-based magnetic tunnel junctions (MTJs). Recently, MTJ-based computing architectures such as logic-in-memory have been proposed and claim superior energy-delay performance over static CMOS. In this paper, we conduct exhaustive energy-performance analysis of an STT-MTJ-based logic-in-memory (LIM-MTJ) 1-bit full adder and compare it with its corresponding CMOS counterpart. Our results show that the LIM-MTJ circuit has no advantage in energy-performance over its equivalent CMOS designs. We also show that the MTJ-based logic circuit requiring frequent MTJ switching during the operation is hardly power efficient.

}, keywords = {psclab}, url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5437290\&tag=1}, author = {Ren, Fengbo and Markovi{\'c}, Dejan} }