@article {379, title = {A 34-FPS 698-GOP/s/W Binarized Deep Neural Network-based Natural Scene Text Interpretation Accelerator for Mobile Edge Computing}, journal = {IEEE Transactions on Industrial Electronics (TIE)}, volume = {66}, year = {2019}, month = {10/2018}, pages = {7407-7416}, abstract = {

The scene text interpretation is a critical part of natural scene interpretation. Currently, most of the existing work is based on high-end GPU implementation, which is commonly used on the server side. However, in IoT application scenarios, the communication overhead from the edge device to the server is quite large, which sometimes even dominates the total processing time. Hence, the edgecomputing oriented design is needed to solve this problem. In this paper, we present an architectural design and implementation of a natural scene text interpretation (NSTI) accelerator, which can classify and localize the text region on pixel-level efficiently in real-time on mobile devices. To target the real-time and low-latency processing, the Binary Convolutional Encoder-decoder Network (B-CEDNet) is adopted as the core architecture to enable massive parallelism due to its binary feature. Massively parallelized computations and a highly pipelined data flow control enhance its latency and throughput performance. In addition, all the binarized intermediate results and parameters are stored on chip to eliminate the power consumption and latency overhead of the off-chip communication. The NSTI accelerator is implemented in a 40nm CMOS technology, which can process scene text images (size of 128x32) at 34 fps and latency of 40 ms for pixelwise interpretation with the pixelwise classification accuracy over 90\% on ICDAR- 03 and ICDAR-13 dataset. The real energy-efficiency is 698 GOP/s/W and the peak energy-efficiency can get up to 7825 GOP/s/W. The proposed accelerator is 7 more energy efficient than its optimized GPU-based implementation counterpart, while maintaining a real-time throughput with latency of 40 ms.

}, keywords = {psclab}, doi = {10.1109/TIE.2018.2875643}, url = {https://ieeexplore.ieee.org/document/8513982}, author = {YIxing Li and Zichuan Liu and Wenye Liu and Yu Jiang and Yongliang Wang and Wang Ling Goh and Hao Yu and Fengbo Ren} } @article {366, title = {A Deep Learning Approach for Targeted Contrast-Enhanced Ultrasound Based Prostate Cancer Detection}, journal = {IEEE/ACM Transactions on Computational Biology and Bioinformatics}, volume = {16}, year = {2019}, month = {05/2018}, pages = {1794-1801}, abstract = {

The important role of angiogenesis in cancer development has driven many researchers to investigate the prospects of noninvasive cancer diagnosis based on the technology of contrast-enhanced ultrasound (CEUS) imaging. This paper presents a deep learning framework to detect prostate cancer in the sequential CEUS images. The proposed method uniformly extracts features from both the spatial and the temporal dimensions by performing three-dimensional convolution operations, which captures the dynamic information of the perfusion process encoded in multiple adjacent frames for prostate cancer detection. The deep learning models were trained and validated against expert delineations over the CEUS images recorded using two types of contrast agents, i.e. the anti-PSMA based agent targeted to prostate cancer cells and the non-targeted blank agent. Experiments showed that the deep learning method achieved over 91\% specificity and 90\% average accuracy over the targeted CEUS images for prostate cancer detection, which was superior (p \< 0.05) than previously reported approaches and implementations.

}, keywords = {psclab}, doi = {10.1109/TCBB.2018.2835444}, url = {https://ieeexplore.ieee.org/document/8357938}, author = {Yujie Feng and Fan Yang and Xichuan Zhou and Yanli Guo and Fang Tang and Fengbo Ren and Jishun Guo and Shuiwang Ji} } @article {9999, title = {An 8-Bit Compressive Sensing ADC With 4GS/s Equivalent Speed Utilizing Self-Timed Pipeline SAR-Binary-Search}, journal = {IEEE Transactions on Circuits and Systems II: Express Briefs}, volume = {63}, year = {2016}, month = {10/2016}, pages = {934-938}, abstract = {

This brief presents a 65nm CMOS single-channel 8- bit ADC compatible for energy-efficient high-speed Compressive Sensing (CS) and Nyquist Sampling (NS). A self-timed pipeline two-stage SAR-Binary-Search (BS) architecture is proposed and integrated with a 4GHz random-matrix clock generator, enabling a physical sampling speed up to 500MS/s with 40.2dB SNDR in NS-mode, and an equivalent speed up to 4GS/s with 36.2dB SNDR in CS-mode, leading to a FOM of 239fJ/conversion-step and 71fJ/conversion-step respectively. A Passive-charge-sharing (PCS) with open-loop (OL) residue-amplifier (RA) technique is proposed to boost the maximum physical sampling speed and the equivalent CS acquisition bandwidth. A reference-voltage fitting calibration scheme is applied to pre-distort inter-stage errors.

}, keywords = {psclab}, author = {Boyu Hu and Fengbo Ren and Zuow-Zun Chen and Xicheng Jiang and Mau-Chung Frank Chang} } @article {9999, title = {9-bit time{\textendash}digital-converter-assisted compressive-sensing analogue{\textendash}digital-converter with 4 GS/s equivalent speed}, journal = {IET Electronics Letters}, volume = {52}, year = {2016}, month = {03/2016}, pages = {430-432}, abstract = {

A novel 9-bit time{\textendash}digital-converter (TDC)-assisted analogue{\textendash}digital-converter (ADC) supporting energy-efficient high-speed compressive-sensing (CS) operation is presented. With a voltage{\textendash}time-converter serving as the cross-domain residue conveyer, the proposed two-stage self-timed pipeline ADC architecture hybrids a voltage-domain comparator-interleaved successive-approximation (SAR) ADC front-end and a time-domain locally readjusted folding two-dimensional Vernier TDC back-end. Implemented in 65 nm CMOS technology, the prototype benefits from both the CS-enabled sub-Nyquist operation and the hybrid quantisation scheme, leading up to 4 GS/s equivalent speed with 34.2 dB signal-noise-distortion-ratio (SNDR) and a figure-of-merit (FOM) of 101 fJ/conversion step.

}, keywords = {psclab}, author = {Boyu Hu and Fengbo Ren and Zuow-Zun Chen and Xicheng Jiang and Mau-Chung Frank Chang} }