@booklet {279, title = {Techniques and systems for local independent failure domains}, year = {2017}, abstract = {

Techniques and systems are described for enabling local independent failure domains in a host server or datacenter environment. Included is a locally-attached independent failure device (LA-IFD) with an independent data buffer and a local communications bus for attaching to a host server. Techniques for a communications protocol between the LA-IFD and its host server are provided, including: receiving a request to write a data segment to persistent storage; synchronously storing the data segment in a buffered data segment at the LA-IFD and initiating an asynchronous update of the data segment at a remote storage system; sending a write acknowledgement indicating completion to the requestor; and, after receiving a completion notification from the remote storage system, removing the buffered data segment from the LA-IFD. In some cases, techniques allow a host server and LA-IFD pair to monitor one another for failures and implement a modified protocol in the event of unavailability.

}, keywords = {other}, author = {Rangaswami, Raju and Biookaghazadeh, Saman and Lyons, Steven} } @article {16, title = {True Energy-performance Analysis Of The MTJ-based Logic-in-memory Architecture (1-bit Full Adder)}, journal = {IEEE Transactions on Electron Devices}, volume = {57}, year = {2010}, month = {Mar.}, pages = {1023{\textendash}1028}, abstract = {

The use of spin-transfer torque (STT) devices for memory design has been a subject of research since the discovery of the STT on MgO-based magnetic tunnel junctions (MTJs). Recently, MTJ-based computing architectures such as logic-in-memory have been proposed and claim superior energy-delay performance over static CMOS. In this paper, we conduct exhaustive energy-performance analysis of an STT-MTJ-based logic-in-memory (LIM-MTJ) 1-bit full adder and compare it with its corresponding CMOS counterpart. Our results show that the LIM-MTJ circuit has no advantage in energy-performance over its equivalent CMOS designs. We also show that the MTJ-based logic circuit requiring frequent MTJ switching during the operation is hardly power efficient.

}, keywords = {psclab}, url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5437290\&tag=1}, author = {Ren, Fengbo and Markovi{\'c}, Dejan} }