@article {18,
	title = {Scalability and Design-space Analysis of A 1T-1MTJ Memory Cell For STT-RAMs},
	journal = {IEEE Transactions on Electron Devices},
	volume = {59},
	year = {2012},
	month = {Jan.},
	pages = {878{\textendash}887},
	abstract = {<p>We present a design-space feasibility region, as a function of magnetic tunnel junction (MTJ) characteristics and target memory specifications, to explore the design margin of a one-transistor-one-magnetic-tunnel-junction (1T-1MTJ) memory cell for spin-transfer torque random access memories (STT-RAMs). Data from measured devices are used to model the statistical variation of an MTJ{\textquoteright}s critical switching current and resistance. The sensitivity of the design space to different design parameters is also analyzed for the scaling of both the MTJ and the underlying transistor technology. A design flow, using a sensitivity-based analysis and an MTJ switching model based on the Landau-Lifshitz-Gilbert equation, is proposed to optimize design margins for gigabit-scale memories. Design points for improved yield, density, and memory performance are extracted from MTJ-compatible complementary metal-oxide-semiconductor (CMOS) technologies for 90-, 65-, 45-, and 32-nm processes. Predictive technology models are used to explore the future scalability of STT-RAMs in upcoming 22- and 16-nm technology nodes. Our analysis shows that, to achieve Flash-like densities ( \&lt;; 6F2) in advanced CMOS technologies, aggressive scaling of the critical switching current density will be required.</p>},
	keywords = {psclab},
	url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6140952},
	author = {Dorrance, Richard and Ren, Fengbo and Toriyama, Yuta and Hafez, Amr Amin and Yang, C-KK and Markovi{\'c}, Dejan}
}
