Energy-performance Characterization of CMOS/Magnetic Tunnel Junction (MTJ) Hybrid Logic Circuits

Magnetic Tunnel Junction (MTJ) devices are CMOS compatible with high stability, high reliability and non-volatility. All these features are promising for building non-volatile CMOS/MTJ hybrid logic circuits that do not consume off-state leakage current and that supports ultra-low-power operation. However, most existing proposals for this purpose so far lack an energy-performance analysis and a comparison to CMOS circuits. In this work, we analyze and compare the energy-performance characteristics of a wide range of CMOS/MTJ hybrid circuits over the device, circuit and architectural levels. This will include device switching energies, logic-in-memory MTJ (LIM-MTJ) logic circuit, two MTJ reading circuits and two CMOS/MTJ hybrid lookup table (LUT) architectures. Our analysis shows that the existing LIM-MTJ logic style has no advantage in energy-performance over its equivalent CMOS design, and that with the switching energy of MTJ considered, the CMOS/MTJ hybrid circuit requiring frequent MTJ switching is hardly energy efficient. Our simulation results also show that the cross-coupled inverter based MTJ reading circuit has 4 times greater performance and 30 times lower energy than the current-mirror sense amplifier based reading circuit. It is also shown that the proposed CMOS/MTJ hybrid LUT based logic architecture, which requires no MTJ switching during logic operations, is able to incorporate the non-volatility of the MTJ to alleviate the leakage problem of CMOS, and to thereby supports ultra-low power operation in advanced technology nodes (32-nm and beyond).